Index: src_plugins/io_eagle/eagle_bin.c =================================================================== --- src_plugins/io_eagle/eagle_bin.c (revision 10475) +++ src_plugins/io_eagle/eagle_bin.c (revision 10476) @@ -1551,7 +1551,7 @@ } else if (strcmp(e->key, "arctype_0_y2") == 0) { egb_node_prop_set(root, "y2", e->value); pcb_trace("Created arc y2: %s\n", e->value); - } /* add width doubling routine here */ + } /* could add width doubling routine here */ } break; /* case -1: break;*/ @@ -1569,7 +1569,7 @@ } else if (strcmp(e->key, "arctype_other_y2") == 0) { egb_node_prop_set(root, "y2", e->value); pcb_trace("Created arc y2: %s\n", e->value); - } /* add width doubling routine here */ + } /* could add width doubling routine here */ } } if (arc_type >= 0) { @@ -1591,7 +1591,7 @@ egb_node_t *drawing = root->first_child; for(n = drawing->first_child, board = NULL; board == NULL && n != NULL; n = next) { - next = n->next; /* need to save this because unlink() will ruin it */ + next = n->next; if (board == NULL && n->id == PCB_EGKW_SECT_BOARD) { pcb_trace("Found PCB_EKGW_SECT_BOARD\n"); board = n; @@ -1607,7 +1607,7 @@ } for(n = el1; n != NULL; n = next) { - next = n->next; /* need to save this because unlink() will ruin it */ + next = n->next; pcb_trace("inspecting el1 subnode: %d\n", n->id); if (n->first_child && n->first_child->id == PCB_EGKW_SECT_ELEMENT2) { pcb_trace("Found PCB_EKGW_SECT_ELEMENT2\n"); @@ -1615,17 +1615,30 @@ for(q = el2->first_child; q != NULL; q = next2) { next2 = q->next; for (e = htss_first(&q->props); e; e = htss_next(&q->props, e)) { - if (strcmp(e->key, "name") == 0) { + if (strcmp(e->key, "name") == 0) { egb_node_prop_set(n, "name", e->value); - pcb_trace("Moved name %s to PCB_EKGW_SECT_ELEMENT\n", e->value); + pcb_trace("Copied name %s to PCB_EKGW_SECT_ELEMENT\n", e->value); } else if (strcmp(e->key, "value") == 0) { egb_node_prop_set(n, "value", e->value); - pcb_trace("Moved value %s to PCB_EKGW_SECT_ELEMENT\n", e->value); + pcb_trace("Copied value %s to PCB_EKGW_SECT_ELEMENT\n", e->value); } } } } + /* we now add element x,y fields to refdes/value element2 node */ + for (e = htss_first(&n->props); e; e = htss_next(&n->props, e)) { + if (strcmp(e->key, "x") == 0) { + egb_node_prop_set(el2, "x", e->value); + pcb_trace("Added element x %s to PCB_EKGW_SECT_ELEMENT2\n", e->value); + } + else if (strcmp(e->key, "y") == 0) { + egb_node_prop_set(el2, "y", e->value); + pcb_trace("Added element y %s to PCB_EKGW_SECT_ELEMENT2\n", e->value); + } + } + /* could potentially add default size, rot to text somewhere around here + or look harder for other optional nodes defining these parameters here */ } return 0; } Index: src_plugins/io_eagle/read.c =================================================================== --- src_plugins/io_eagle/read.c (revision 10475) +++ src_plugins/io_eagle/read.c (revision 10476) @@ -642,7 +642,7 @@ if (lt != -1) { pcb_trace("Found wire type %ld\n", lt); } - else if (lt > 0 || lt == -127) { + if (lt > 0 || lt == -127) { pcb_trace("Using circle routine to process wire type 'lt'\n"); return eagle_read_circle(st, subtree, obj, type); } @@ -863,8 +863,6 @@ const char *cont; #warning subc TODO subcircuits will allow distinct refdes, descr and value text field attributes -/* pcb_text_t *t;*/ -/* pcb_element_t *elem = obj;*/ for(n = CHILDREN(subtree); n != NULL; n = NEXT(n)) if (IS_TEXT(n)) @@ -874,13 +872,11 @@ return 0; if (STRCMP(cont, ">NAME") == 0) { -/* t = &elem->Name[PCB_ELEMNAME_IDX_REFDES];*/ size = eagle_get_attrc(st, subtree, "size", EAGLE_TEXT_SIZE_100); st->refdes_scale = (int)(((double)size/ (double)EAGLE_TEXT_SIZE_100) * 100.0); st->refdes_x = eagle_get_attrc(st, subtree, "x", 0); st->refdes_y = eagle_get_attrc(st, subtree, "y", 0); } else if (STRCMP(cont, ">VALUE") == 0) { -/* t = &elem->Name[PCB_ELEMNAME_IDX_VALUE];*/ size = eagle_get_attrc(st, subtree, "size", EAGLE_TEXT_SIZE_100); st->value_scale = (int)(((double)size/ (double)EAGLE_TEXT_SIZE_100) * 100.0); st->value_x = eagle_get_attrc(st, subtree, "x", 0); @@ -908,6 +904,13 @@ {NULL, NULL} #warning subc TODO can dd polygon to package }; + /* zero these out before current pkg read */ + st->refdes_x = 0; + st->refdes_y = 0; + st->refdes_scale = 0; + st->value_x = 0; + st->value_y = 0; + st->value_scale = 0; return eagle_foreach_dispatch(st, CHILDREN(subtree), disp, elem, IN_ELEM); } @@ -1103,29 +1106,32 @@ { int direction = 0; pcb_flag_t TextFlags = pcb_no_flags(); + pcb_coord_t size; - /*x += def_text->X; - y += def_text->Y + EAGLE_TEXT_SIZE_100; */ + x += def_text->X; + y += def_text->Y + EAGLE_TEXT_SIZE_100; for(nd = CHILDREN(nd); nd != NULL; nd = NEXT(nd)) { const char *this_attr = eagle_get_attrs(st, nd, "name", ""); - if ((STRCMP(NODENAME(nd), "attribute") == 0) && (strcmp(attname, this_attr) == 0)) { + if (((STRCMP(NODENAME(nd), "attribute") == 0) || + (STRCMP(NODENAME(nd), "element2") == 0) ) + && (strcmp(attname, this_attr) == 0)) { direction = eagle_rot2steps(eagle_get_attrs(st, nd, "rot", NULL)); if (direction < 0) direction = 0; -/* size = eagle_get_attrc(st, nd, "size", -1);*/ - x += eagle_get_attrc(st, nd, "x", x); - y += eagle_get_attrc(st, nd, "y", y); + size = eagle_get_attrc(st, nd, "size", EAGLE_TEXT_SIZE_100); break; } } #warning subc TODO can have unique text scaling in subcircuits -/* + int TextScale = (def_text->Scale == 0 ? 100 : def_text->Scale); - pcb_coord_t size; - if (size >= 0) +#warning TODO scaling not behaving due to size read issue so hard wired for now +/* if (size >= 0) TextScale = (int)(((double)size/ (double)EAGLE_TEXT_SIZE_100) * 100.0); - pcb_trace("About to use text scale %d for element.\n", TextScale); +*/ + TextScale = 100; /* hardwired for now */ +/* pcb_trace("About to use text scale %d for element.\n", TextScale); pcb_element_text_set(text, pcb_font(st->pcb, 0, 1), x, y, direction, str, TextScale, TextFlags); */