Index: trunk/tests/RTT/ref/elem_pins.gbr/elem_pins.topsilk.gbr
===================================================================
--- trunk/tests/RTT/ref/elem_pins.gbr/elem_pins.topsilk.gbr	(nonexistent)
+++ trunk/tests/RTT/ref/elem_pins.gbr/elem_pins.topsilk.gbr	(revision 11786)
@@ -0,0 +1,45 @@
+G04 start of page 5 for group 1 layer_idx 8 *
+G04 Title: pins with different shapes, top_silk *
+G04 Creator: <version>
+G04 CreationDate: <date>
+G04 For: TEST *
+G04 Format: Gerber/RS-274X *
+G04 PCB-Dimensions: 50000 50000 *
+G04 PCB-Coordinate-Origin: lower left *
+%MOIN*%
+%FSLAX25Y25*%
+%LNTOPSILK*%
+%ADD17C,0.0070*%
+%ADD16C,0.0100*%
+G54D16*X2500Y42500D02*Y32500D01*
+X42500D02*X2500D01*
+X42500D02*Y42500D01*
+X2500D02*X17500D01*
+X27500D02*X42500D01*
+X17500D02*G75*G03X27500Y42500I5000J0D01*G01*
+X2500Y22500D02*Y12500D01*
+X42500D02*X2500D01*
+X42500D02*Y22500D01*
+X2500D02*X17500D01*
+X27500D02*X42500D01*
+X17500D02*G75*G03X27500Y22500I5000J0D01*G01*
+G54D17*X7500Y47500D02*Y44000D01*
+X8000Y43500D01*
+X9000D01*
+X9500Y44000D01*
+Y47500D02*Y44000D01*
+X10700Y46700D02*X11500Y47500D01*
+Y43500D01*
+X10700D02*X12200D01*
+X7500Y27500D02*Y24000D01*
+X8000Y23500D01*
+X9000D01*
+X9500Y24000D01*
+Y27500D02*Y24000D01*
+X10700Y27000D02*X11200Y27500D01*
+X12700D01*
+X13200Y27000D01*
+Y26000D01*
+X10700Y23500D02*X13200Y26000D01*
+X10700Y23500D02*X13200D01*
+M02*
Index: trunk/tests/RTT/ref/elem_sides_trh.gbr/elem_sides_trh.bottomsilk.gbr
===================================================================
--- trunk/tests/RTT/ref/elem_sides_trh.gbr/elem_sides_trh.bottomsilk.gbr	(nonexistent)
+++ trunk/tests/RTT/ref/elem_sides_trh.gbr/elem_sides_trh.bottomsilk.gbr	(revision 11786)
@@ -0,0 +1,31 @@
+G04 start of page 6 for group 12 layer_idx 7 *
+G04 Title: thru-hole elements on both sides, bottom_silk *
+G04 Creator: <version>
+G04 CreationDate: <date>
+G04 For: TEST *
+G04 Format: Gerber/RS-274X *
+G04 PCB-Dimensions: 50000 50000 *
+G04 PCB-Coordinate-Origin: lower left *
+%MOIN*%
+%FSLAX25Y25*%
+%LNBOTTOMSILK*%
+%ADD19C,0.0070*%
+%ADD18C,0.0100*%
+G54D18*X5000Y10000D02*Y20000D01*
+X45000D02*X5000D01*
+X45000D02*Y10000D01*
+X5000D02*X20000D01*
+X30000D02*X45000D01*
+X30000D02*G75*G03X20000Y10000I-5000J0D01*G01*
+G54D19*X10000Y5000D02*Y8500D01*
+X10500Y9000D01*
+X11500D01*
+X12000Y8500D01*
+Y5000D02*Y8500D01*
+X13200Y5500D02*X13700Y5000D01*
+X15200D01*
+X15700Y5500D01*
+Y6500D01*
+X13200Y9000D02*X15700Y6500D01*
+X13200Y9000D02*X15700D01*
+M02*
Index: trunk/tests/RTT/ref/elem_sides_trh.gbr/elem_sides_trh.topsilk.gbr
===================================================================
--- trunk/tests/RTT/ref/elem_sides_trh.gbr/elem_sides_trh.topsilk.gbr	(nonexistent)
+++ trunk/tests/RTT/ref/elem_sides_trh.gbr/elem_sides_trh.topsilk.gbr	(revision 11786)
@@ -0,0 +1,28 @@
+G04 start of page 5 for group 1 layer_idx 8 *
+G04 Title: thru-hole elements on both sides, top_silk *
+G04 Creator: <version>
+G04 CreationDate: <date>
+G04 For: TEST *
+G04 Format: Gerber/RS-274X *
+G04 PCB-Dimensions: 50000 50000 *
+G04 PCB-Coordinate-Origin: lower left *
+%MOIN*%
+%FSLAX25Y25*%
+%LNTOPSILK*%
+%ADD17C,0.0070*%
+%ADD16C,0.0100*%
+G54D16*X5000Y40000D02*Y30000D01*
+X45000D02*X5000D01*
+X45000D02*Y40000D01*
+X5000D02*X20000D01*
+X30000D02*X45000D01*
+X20000D02*G75*G03X30000Y40000I5000J0D01*G01*
+G54D17*X10000Y45000D02*Y41500D01*
+X10500Y41000D01*
+X11500D01*
+X12000Y41500D01*
+Y45000D02*Y41500D01*
+X13200Y44200D02*X14000Y45000D01*
+Y41000D01*
+X13200D02*X14700D01*
+M02*
Index: trunk/tests/RTT/ref/netlist.gbr/netlist.topsilk.gbr
===================================================================
--- trunk/tests/RTT/ref/netlist.gbr/netlist.topsilk.gbr	(nonexistent)
+++ trunk/tests/RTT/ref/netlist.gbr/netlist.topsilk.gbr	(revision 11786)
@@ -0,0 +1,28 @@
+G04 start of page 5 for group 1 layer_idx 8 *
+G04 Title: board with minimal netlist, top_silk *
+G04 Creator: <version>
+G04 CreationDate: <date>
+G04 For: TEST *
+G04 Format: Gerber/RS-274X *
+G04 PCB-Dimensions: 50000 50000 *
+G04 PCB-Coordinate-Origin: lower left *
+%MOIN*%
+%FSLAX25Y25*%
+%LNTOPSILK*%
+%ADD17C,0.0070*%
+%ADD16C,0.0100*%
+G54D16*X5000Y37500D02*Y17500D01*
+X45000D02*X5000D01*
+X45000D02*Y37500D01*
+X5000D02*X20000D01*
+X30000D02*X45000D01*
+X20000D02*G75*G03X30000Y37500I5000J0D01*G01*
+G54D17*X10000Y42500D02*Y39000D01*
+X10500Y38500D01*
+X11500D01*
+X12000Y39000D01*
+Y42500D02*Y39000D01*
+X13200Y41700D02*X14000Y42500D01*
+Y38500D01*
+X13200D02*X14700D01*
+M02*
Index: trunk/tests/RTT/ref/netlist_ba.gbr/netlist_ba.topsilk.gbr
===================================================================
--- trunk/tests/RTT/ref/netlist_ba.gbr/netlist_ba.topsilk.gbr	(nonexistent)
+++ trunk/tests/RTT/ref/netlist_ba.gbr/netlist_ba.topsilk.gbr	(revision 11786)
@@ -0,0 +1,28 @@
+G04 start of page 5 for group 1 layer_idx 8 *
+G04 Title: board with minimal netlist and some back-annotation changes, top_silk *
+G04 Creator: <version>
+G04 CreationDate: <date>
+G04 For: TEST *
+G04 Format: Gerber/RS-274X *
+G04 PCB-Dimensions: 50000 50000 *
+G04 PCB-Coordinate-Origin: lower left *
+%MOIN*%
+%FSLAX25Y25*%
+%LNTOPSILK*%
+%ADD17C,0.0070*%
+%ADD16C,0.0100*%
+G54D16*X5000Y37500D02*Y17500D01*
+X45000D02*X5000D01*
+X45000D02*Y37500D01*
+X5000D02*X20000D01*
+X30000D02*X45000D01*
+X20000D02*G75*G03X30000Y37500I5000J0D01*G01*
+G54D17*X10000Y42500D02*Y39000D01*
+X10500Y38500D01*
+X11500D01*
+X12000Y39000D01*
+Y42500D02*Y39000D01*
+X13200Y41700D02*X14000Y42500D01*
+Y38500D01*
+X13200D02*X14700D01*
+M02*