Index: trunk/src/route-rnd/regression/crbs/bas_smd_side.tdx
===================================================================
--- trunk/src/route-rnd/regression/crbs/bas_smd_side.tdx	(nonexistent)
+++ trunk/src/route-rnd/regression/crbs/bas_smd_side.tdx	(revision 1464)
@@ -0,0 +1,48 @@
+tEDAx v1
+
+begin stackup v1 board_stackup
+ layer 3.top_copper top copper
+  lprop 3.top_copper display-color #8b2323
+ layer 8.bottom_copper bottom copper
+  lprop 8.bottom_copper display-color #3a5fcd
+end stackup
+
+begin polyline v1 pstk_0x55671ff80620_0x55671fe1d370
+ v -0.94996 -0.649986
+ v -0.94996 0.649986
+ v 0.94996 0.649986
+ v 0.94996 -0.649986
+end polyline
+begin polyline v1 pstk_0x55671ff81800_0x55671fe1d370
+ v -0.94996 -0.649986
+ v -0.94996 0.649986
+ v 0.94996 0.649986
+ v 0.94996 -0.649986
+end polyline
+begin layernet v1 3.top_copper
+ poly pcb/48/68 pcbrnd2 tmd pstk_0x55671ff80620_0x55671fe1d370 2.54 4.90474
+ poly pcb/48/69 pcbrnd1 tmd pstk_0x55671ff81800_0x55671fe1d370 2.54 1.905
+end layernet
+
+begin polyline v1 pstk_0x55671ff887d0_0x55671fe1d570
+ v -0.94996 -0.649986
+ v -0.94996 0.649986
+ v 0.94996 0.649986
+ v 0.94996 -0.649986
+end polyline
+begin polyline v1 pstk_0x55671ff89850_0x55671fe1d570
+ v -0.94996 -0.649986
+ v -0.94996 0.649986
+ v 0.94996 0.649986
+ v 0.94996 -0.649986
+end polyline
+begin layernet v1 8.bottom_copper
+ poly pcb/71/91 pcbrnd1 tmd pstk_0x55671ff887d0_0x55671fe1d570 7.62 4.90474
+ poly pcb/71/92 pcbrnd2 tmd pstk_0x55671ff89850_0x55671fe1d570 7.62 1.905
+end layernet
+
+
+begin route_req v1 -
+ stackup board_stackup
+ route_all
+end route_req
Index: trunk/src/route-rnd/regression/crbs/index.in
===================================================================
--- trunk/src/route-rnd/regression/crbs/index.in	(revision 1463)
+++ trunk/src/route-rnd/regression/crbs/index.in	(revision 1464)
@@ -20,6 +20,12 @@
 @ bas_steiner
 Adding a junction ("Steiner point") can reduce total wire length.
 
+@ bas_smd_side
+SMD components may end up on either side of the board; add vias as
+needed to ensure pads are connected on the right side. Via placement
+is one of the weaknesses of the original PhD thesis, which shows on
+this example: with more symmetrical placement total wire length could
+have been minimized.
 
 @ pcb_existing
 A board with a few tracks already existing. Crbs will not move those