- 
- 
- 
- 
- 
-Fonts are always embedded in the design file in order to guarantee that the file can be ported and will look the same on different hosts. @@ -195,8 +195,7 @@ automatically inserted around objects on the same layer group:
Overlapping or touching polygons are not automatically merged. An object @@ -204,6 +203,11 @@ if there are multiple such polygons overlapping under the objects (on the same layer group), all such polygons get the clearance cutout.
+If a polygon has the "clearpolypoly" flag set, it clears any other polygon +that does not have the "clearpolypoly" flag set but has the +"clearpoly" set. In other words, a "clearpolypoly" polygon behaves the same +as a line/arc that has the "clearline" flag. +
If a polygon is cut into multiple islands, the behavior depends on the "fullpoly" flag of the polygon. If it is not set (default), only the largest island is kept, else all islands are kept. In the "fullpoly" mode islands @@ -238,50 +242,50 @@ Bug: copper text can not participate in short circuits, the galvanic connection checker code skips texts. -
A via is an electrically connected hole that connects copper rings to multiple -layers. Thermal relief styles are available to both pads and pins, and the shape -styles of a via are available to pins. Since a via hole always punches all layer -groups and applies the same ring style on any outside layer groups, blind or -buried vias and individually defined layer pad stacks (e.g. with changing ring -shape per layer) are not possible using the via object. +layers. In pcb-rnd, a via is always implemented using a +padstack.
-A thermal relief property is added to the copper rings of a via when it is -connected to the surrounding polygon of any individual layer. Physical designs -may use thermal reliefs to enable easy hand soldering, or reduce occurrence of -tombstoning in automated production. +A hole is a special case of a padstack: it has +an unplated hole and typically does not have copper pad shapes but should +have mask cutout shape.
-The following thermal relief options are available: -
| Thermal Relief | Appearance - |
|---|---|
| no connection |
- |
| solid |
- |
| round x 90 |
- |
| round x 45 |
- |
| crossbar x 90 |
- |
| crossbar x 45 |
- |
-A variety of pin pad shapes are also available to the pcb-rnd user. The copper -annulus (ring) on the outside layer groups is selectable from a predefined set -of shapes that provide solderability or can be used to indicate a special pin. -Flags in the via object define the shape used. -
| Shape | Appearance - |
|---|---|
| ring (default) | 
- |
| square | 
- |
| octagon | 
- |
| asymmetric | 
- |
+A mark or target (e.g. for layer alignment) is usually realized as a + subcircuit it has more complex graphics that +doesn't fit in a padstack. +
+Holes, test points/pads and fiducials are often realized within a + subcircuit , especially if they have a refdes +and present on the schematics. -
+A subc (subcircuit) is a group of objects with its own, local layer +information. All layers of a subc are bound layers, that is, the user +is free to choose on which actual board layer it is placed on. +There is no limitation on what layers or objects a subc can contain. +
+The main uses of subc are: +
-An element is an instance of a footprint that is already placed on the -board or loaded into a paste buffer. +A subcircuit may be an instance (copy) of a footprint. The subcircuit is +placed on the board or loaded into a paste buffer (the footprint lives in +the footprint library).
In the footprint form the construct is small and flexible. It describes @@ -290,128 +294,42 @@ it doesn't have font and the refdes is random.
-When the footprint is loaded, it becomes an element. The element inherits all +When the footprint is loaded, it becomes an subcircuit. The subcircuit inherits all the physical properties and the blank details are filled in with the data taken -from the current board: the layer binding is done, all parts of the element +from the current board: the layer binding is done, all parts of the subcircuit lands on a specific board layer; the refdes is rendered using the font in the current board.
-The footprint -> element instantiation is also a copy. Once the element -is created from a footprint, the element is a self-containing object and +The footprint -> subcircuit instantiation is also a copy. Once the subcircuit +is created from a footprint, the subcircuit is a self-containing object and does not have any direct reference to the footprint it was once derived from. -Changes to the original footprint will not affect the elements. +Changes to the original footprint will not affect the subcircuits.
In other words, a footprint is an abstract recipe, part of a -library, while an element is a land pattern already embedded in a +library, while an subcircuit is a land pattern already embedded in a specific design and describes actual copper and silk.
-Currently an element or footprint can contain the following objects: -
-An element has the following properties: +Commonly used subcircuit attributes:
| element property | description - |
|---|---|
| name: refdes | unique identifier, e.g. "C42" - |
| name: value | informal value, e.g. "15 pF" - |
| name: description | informal element or footprint description, e.g. "1206" + |
| subcircuit attribute | description + |
| name: refdes | unique identifier, e.g. "C42" - pcb-rnd code will use this when present + |
| name: value | informal value, e.g. "15 pF" + |
| name: footprint | informal footprint description, e.g. "1206" |
-Extra object flags: -
-
| name | description - |
|---|---|
| ONSOLDER | when set, the element is on the bottom side, else it's on the top side - |
| NONETLIST | when set, the element is not intended to be on the netlist; useful for elements that are not present on the schematics and are placed during the layout design - |
| HIDENAME | when set the name of the element is hidden - |
| DISPLAYNAME | when set the names of pins are shown - |
-
| name | description - |
|---|---|
| name | pin name, e.g. "base" - |
| number | pin name, e.g. 2 - |
| intconn | internal element connections (see section TODO) - |
-
| name | description - |
|---|---|
| via flags | (extra flags listed for vias are applicable to pins too) - |
| WARN | the pin contributes to a short circuit ("orange mark") - |
-A pad is an smd pad of an element. It is modelled as a line segment, usually -with square cap - this makes the pad look like a rectangle. A pad has -the same metadata and capabilities as pins. Overlapping pads are supported. -A pad is always on either the top or the bottom copper layer group. -
-A pad has the following properties: -
-
| name | description - |
|---|---|
| name | pin name, e.g. "base" - |
| number | pin name, e.g. 2 - |
| intconn | internal element connections (see section TODO) - |
-
| name | description - |
|---|---|
| via flags | (extra flags listed for vias are applicable to pins too) - |
| WARN | the pin contributes to a short circuit ("orange mark") - |
| EDGE2 | indicates that the second point is closer to the edge. For pins, indicates that the pin is closer to a horizontal edge and thus pinout text should be vertical. (Padr.Point2 is closer to outside edge also pinout text for pins is vertical) - |
-A subc (subcircuit) is a group of objects with its own, local layer -information. All layers of a subc are bound layers, that is, the user -is free to choose on which actual board layer it is placed on. -There is no limitation on what layers or objects a subc can contain. -
-The main uses of subc are: -
When a subcircuit is a footprint, it normally has the refdes attribute set. Refdes is the name that identifies the part on the netlist. Some objects of a footprint will have the term attribute to turn those object into @@ -427,13 +345,17 @@ U5-3 means "the object(s) whose term attribute is 3 within the subcircuit whose refdes attribute is 'U5'". -
-Compared to subcircuits as footprint, a repetitive module will not have -a refdes attribute and will not have terminals. +If the repetitive module is specified as a refdes-named device on +the schematics, it is really just a footprint. Else it is a non-footprint +subcircuit. +
+Compared to subcircuits as footprint, a non-footprint subcircuit will not have +a refdes attribute and will not have terminals. It will also have the +nonetlist flag set. - -
A pad stack is a generic pin/pad/via object that may contain any combination of: @@ -540,9 +462,26 @@ possible to have different clearance for internal layers, for example.
Each padstack reference has a per board layer list of thermal relief types. +
+A thermal relief property is added to the copper rings of a via when it is +connected to the surrounding polygon of any individual layer. Physical designs +may use thermal reliefs to enable easy hand soldering, or reduce occurrence of +tombstoning in automated production. +
+The following thermal relief options are available: +
| Thermal Relief | Appearance + |
|---|---|
| no connection |
+ |
| solid |
+ |
| round x 90 |
+ |
| round x 45 |
+ |
| crossbar x 90 |
+ |
| crossbar x 45 |
+ |
A rat line represents a logical connection that is not yet realized in copper. It requires a loaded netlist for generation, and relies on calculations for any @@ -550,11 +489,11 @@ connections are straight line connections between the terminals of any two drawing primitives that aren't yet connected -
A netlist is a list of named logical networks. Each network is a list of netlist terminals that should be connected. A netlist terminal is a pair -of element-refdes and pin-number (or pad-number). Thus a typical netlist +of subcircuit-refdes and pin-number (or pad-number). Thus a typical netlist looks like the following:
-The netlist assumes element refdes are unique. If an element has multiple -instances of the same pin (or pad) number, the engine picks one randomly and -assumes there's an invisible, internal connection within the element. +The netlist assumes subcircuit refdes are unique. If a subcircuit has multiple +instances of the same terminal number, the engine picks one randomly and +assumes there's an invisible, internal connection within the subcircuit.
Rat lines can be regenerated from the current netlist for missing connections. Connections that are realized in copper but not present on the netlist, pcb-rnd @@ -592,14 +531,14 @@ process is called "forward annotation".
It is also possible to make changes to the netlist from within pcb-rnd: -pins can be swapped, element packages replaced using back annotation -actions. Such actions will keep a list of intended netlist and element +terminals can be swapped, subcircuit footprint replaced using back annotation +actions. Such actions will keep a list of intended netlist and subcircuit changes, called the netlist patch. Pcb-rnd will keep these changes even if a new version of the netlist is imported. It is possible to export the netlist patch that can be imported in the schematics editor to change the schematics - this process is called "back annotation". A new forward annotation from the schematics editor to pcb-rnd will then cancel -the netlist/element changes as the new netlist import netlist matches +the netlist/subcircuit changes as the new netlist import netlist matches the intended (changed) netlist.