-A via is an electrically connected hole that connects copper rings to multiple -layers. In pcb-rnd, a via is always implemented using a -padstack. -
-A hole is a special case of a padstack: it has -an unplated hole and typically does not have copper pad shapes but should -have mask cutout shape. -
-A test point or test pad is a padstack that has -copper shape only on one of the outer copper layer and a mask cutout shape -over that layer. -
-A fiducial mark is a special case of a padstack -very similar to the test point/pad. -
-A mark or target (e.g. for layer alignment) is usually realized as a - subcircuit it has more complex graphics that -doesn't fit in a padstack. -
-Holes, test points/pads and fiducials are often realized within a - subcircuit , especially if they have a refdes -and present on the schematics. - -
A subc (subcircuit) is a group of objects with its own, local layer information. All layers of a subc are bound layers, that is, the user @@ -280,7 +255,7 @@
A subcircuit may be an instance (copy) of a footprint. The subcircuit is @@ -345,7 +320,7 @@ U5-3 means "the object(s) whose term attribute is 3 within the subcircuit whose refdes attribute is 'U5'". -
If the repetitive module is specified as a refdes-named device on the schematics, it is really just a footprint. Else it is a non-footprint @@ -355,7 +330,7 @@ a refdes attribute and will not have terminals. It will also have the nonetlist flag set. -
A pad stack is a generic pin/pad/via object that may contain any combination of: @@ -481,7 +456,7 @@ -
A rat line represents a logical connection that is not yet realized in copper. It requires a loaded netlist for generation, and relies on calculations for any @@ -489,7 +464,7 @@ connections are straight line connections between the terminals of any two drawing primitives that aren't yet connected -
A netlist is a list of named logical networks. Each network is a list of netlist terminals that should be connected. A netlist terminal is a pair @@ -541,8 +516,50 @@ the netlist/subcircuit changes as the new netlist import netlist matches the intended (changed) netlist. -
+The following objects are commonly used in the industry, but have no +special implementation in pcb-rnd but are created by using the above +objects. + +
+A via is an electrically connected hole that connects copper rings to multiple +layers. In pcb-rnd, a via is always implemented using a +padstack. + +
+A hole is a special case of a padstack: it has +an unplated hole and typically does not have copper pad shapes but should +have mask cutout shape. + +
+A test point or test pad is a padstack that has +copper shape only on one of the outer copper layer and a mask cutout shape +over that layer. + +
+A fiducial mark is a special case of a padstack +very similar to the test point/pad. + +
+Holes, test points/pads and fiducials are often realized within a + subcircuit , especially if they have a refdes +and present on the schematics. However, the only way to implement a hole +is using a padstack, so the resulting subcircuit for holes and test pins +will always have at least one padstack. + +
| Physical board | pcb-rnd | Description @@ -560,3 +577,4 @@ |
|---|---|---|
| Paste (paste stencil) | Layer group with implicit and potential explicit content | design layers available: automatic, additive, subtractive |
| N/A, or poss. net/circuit | Rats | assistive layer automatically generated with netlist and copper layer group connection data |