Index: trunk/src/gui_act.c
===================================================================
--- trunk/src/gui_act.c	(revision 16177)
+++ trunk/src/gui_act.c	(revision 16178)
@@ -1451,12 +1451,13 @@
 				return 1;
 			}
 			switch(*sbit) {
-				case '+': g->type |= bit; break;
-				case '-': g->type &= ~bit; break;
+				case '+': g->ltype |= bit; break;
+				case '-': g->ltype &= ~bit; break;
 			}
 			interactive = 0;
 			pcb_board_set_changed_flag(pcb_true);
 		}
+#warning layer TODO:
 #if 0
 		else if (strncmp(argv[n], "attrib", 6) == 0) {
 			char *key, *val;
Index: trunk/src/layer.c
===================================================================
--- trunk/src/layer.c	(revision 16177)
+++ trunk/src/layer.c	(revision 16178)
@@ -389,7 +389,7 @@
 	/* reset layer groups */
 	for(n = 0; n < PCB_MAX_LAYERGRP; n++) {
 		pcb->LayerGroups.grp[n].len = 0;
-		pcb->LayerGroups.grp[n].type = 0;
+		pcb->LayerGroups.grp[n].ltype = 0;
 		pcb->LayerGroups.grp[n].valid = 0;
 	}
 	pcb->LayerGroups.len = 0;
@@ -498,7 +498,7 @@
 	lp->meta.real.color = conf_core.appearance.color.layer[idx];
 	lp->meta.real.selected_color = conf_core.appearance.color.layer_selected[idx];
 	if ((gid >= 0) && (pcb->LayerGroups.grp[gid].len == 0)) { /*When adding the first layer in a group, set up comb flags automatically */
-		switch((pcb->LayerGroups.grp[gid].type) & PCB_LYT_ANYTHING) {
+		switch((pcb->LayerGroups.grp[gid].ltype) & PCB_LYT_ANYTHING) {
 			case PCB_LYT_MASK:  lp->comb = PCB_LYC_AUTO | PCB_LYC_SUB; break;
 			case PCB_LYT_SILK:  lp->comb = PCB_LYC_AUTO;
 			case PCB_LYT_PASTE: lp->comb = PCB_LYC_AUTO;
@@ -946,7 +946,7 @@
 		pcb_layergrp_id_t gid = pcb->Data->Layer[*cache].meta.real.grp;
 		if ((gid >= 0) && (gid < pcb->LayerGroups.len)) {
 			g = &(pcb->LayerGroups.grp[gid]);
-			if ((g->type & loc) && (g->type & typ) && (g->lid[0] == *cache))
+			if ((g->ltype & loc) && (g->ltype & typ) && (g->lid[0] == *cache))
 				return *cache;
 		}
 	}
Index: trunk/src/layer_grp.c
===================================================================
--- trunk/src/layer_grp.c	(revision 16177)
+++ trunk/src/layer_grp.c	(revision 16178)
@@ -143,7 +143,7 @@
 	if ((gid < 0) || (gid >= pcb->LayerGroups.len))
 		return 0;
 
-	return pcb->LayerGroups.grp[gid].type;
+	return pcb->LayerGroups.grp[gid].ltype;
 }
 
 const char *pcb_layergrp_name(pcb_board_t *pcb, pcb_layergrp_id_t gid)
@@ -161,7 +161,7 @@
 	pcb_layergrp_t *g = &pcb->LayerGroups.grp[num];
 
 	/* some layers are never empty */
-	if (g->type & PCB_LYT_MASK)
+	if (g->ltype & PCB_LYT_MASK)
 		return pcb_false;
 
 	if (!pcb_pstk_is_group_empty(pcb, num))
@@ -244,7 +244,7 @@
 {
 	int n;
 	for(n = 0; n < stack->len; n++)
-		if ((stack->grp[n].type & loc) && (stack->grp[n].type & typ))
+		if ((stack->grp[n].ltype & loc) && (stack->grp[n].ltype & typ))
 			return &(stack->grp[n]);
 	return NULL;
 }
@@ -275,7 +275,7 @@
 
 	/* seek the bottom copper layer */
 	for(bl = stack->len; bl >= 0; bl--) {
-		if ((stack->grp[bl].type & PCB_LYT_BOTTOM) && (stack->grp[bl].type & PCB_LYT_COPPER)) {
+		if ((stack->grp[bl].ltype & PCB_LYT_BOTTOM) && (stack->grp[bl].ltype & PCB_LYT_COPPER)) {
 
 			/* insert a new internal layer: move existing layers to make room */
 			for(n = stack->len-1; n >= bl; n--)
@@ -284,11 +284,11 @@
 			stack->len += room;
 
 			stack->grp[bl].name = pcb_strdup("Intern");
-			stack->grp[bl].type = PCB_LYT_INTERN | PCB_LYT_COPPER;
+			stack->grp[bl].ltype = PCB_LYT_INTERN | PCB_LYT_COPPER;
 			stack->grp[bl].valid = 1;
 			bl++;
 			if (!omit_substrate) {
-				stack->grp[bl].type = PCB_LYT_INTERN | PCB_LYT_SUBSTRATE;
+				stack->grp[bl].ltype = PCB_LYT_INTERN | PCB_LYT_SUBSTRATE;
 				stack->grp[bl].valid = 1;
 			}
 			return &stack->grp[bl-1];
@@ -465,7 +465,7 @@
 {
 	pcb_layer_stack_t *LayerGroup = &pcb->LayerGroups;
 	pcb_layergrp_t *g = pcb_get_grp(LayerGroup, PCB_LYT_ANYWHERE, PCB_LYT_OUTLINE);
-	if ((g != NULL) && (g[1].type & PCB_LYT_SUBSTRATE)) {
+	if ((g != NULL) && (g[1].ltype & PCB_LYT_SUBSTRATE)) {
 		pcb_layergrp_id_t gid = g - LayerGroup->grp + 1;
 		pcb_layergrp_del(pcb, gid, 0);
 	}
@@ -473,8 +473,8 @@
 
 void pcb_layergrp_fix_turn_to_outline(pcb_layergrp_t *g)
 {
-	g->type |= PCB_LYT_OUTLINE;
-	g->type &= ~PCB_LYT_COPPER;
+	g->ltype |= PCB_LYT_OUTLINE;
+	g->ltype &= ~PCB_LYT_COPPER;
 	free(g->name);
 	g->name = pcb_strdup("global_outline");
 }
@@ -517,7 +517,7 @@
 					if (lids[n] < 0)
 						continue;
 					if (LAYER_IS_OUTLINE(lids[n])) {
-						if (g->type & PCB_LYT_INTERN)
+						if (g->ltype & PCB_LYT_INTERN)
 							pcb_layergrp_fix_turn_to_outline(g);
 						else
 							pcb_message(PCB_MSG_ERROR, "outline layer can not be on the solder or component side - converting it into a copper layer\n");
@@ -628,7 +628,7 @@
 		g->name = pcb_strdup(gname); \
 	else \
 		g->name = NULL; \
-	g->type = flags; \
+	g->ltype = flags; \
 	newg->len++; \
 } while(0)
 
@@ -656,7 +656,7 @@
 {
 	pcb_layergrp_id_t gid;
 	for(gid = 0; gid < pcb->LayerGroups.len; gid++)
-		if ((pcb->LayerGroups.grp[gid].type & PCB_LYT_SILK) && (pcb->LayerGroups.grp[gid].len == 0))
+		if ((pcb->LayerGroups.grp[gid].ltype & PCB_LYT_SILK) && (pcb->LayerGroups.grp[gid].len == 0))
 			pcb_layer_create(pcb, gid, "silk");
 }
 
@@ -700,7 +700,7 @@
 	for(gid = gid1; gid != gid2; gid += d) {
 		if ((gid < 0) || (gid >= pcb->LayerGroups.len))
 			return -1;
-		if ((pcb->LayerGroups.grp[gid].type & mask) == mask)
+		if ((pcb->LayerGroups.grp[gid].ltype & mask) == mask)
 			cnt++;
 	}
 	*diff = cnt;
@@ -727,7 +727,7 @@
 	for(gid += d;; gid += d) {
 		if ((gid < 0) || (gid >= pcb->LayerGroups.len))
 			return -1;
-		if ((pcb->LayerGroups.grp[gid].type & mask) == mask) {
+		if ((pcb->LayerGroups.grp[gid].ltype & mask) == mask) {
 			steps--;
 			if (steps == 0)
 				return gid;
@@ -741,10 +741,10 @@
 	pcb_layergrp_id_t g;
 	for(g = 0; g < pcb->LayerGroups.len-2; g++) {
 		pcb_layergrp_t *g0 = &pcb->LayerGroups.grp[g], *g1 = &pcb->LayerGroups.grp[g+1];
-		if ((g < pcb->LayerGroups.len-3) && (g1->type & PCB_LYT_OUTLINE)) g1++;
-		if ((g0->type & PCB_LYT_COPPER) && (g1->type & PCB_LYT_COPPER)) {
+		if ((g < pcb->LayerGroups.len-3) && (g1->ltype & PCB_LYT_OUTLINE)) g1++;
+		if ((g0->ltype & PCB_LYT_COPPER) && (g1->ltype & PCB_LYT_COPPER)) {
 			pcb_layergrp_t *ng = pcb_layergrp_insert_after(pcb, g);
-			ng->type = PCB_LYT_INTERN | PCB_LYT_SUBSTRATE;
+			ng->ltype = PCB_LYT_INTERN | PCB_LYT_SUBSTRATE;
 			ng->name = pcb_strdup("implicit_subst");
 			ng->valid = 1;
 		}
@@ -757,7 +757,7 @@
 	static char *anon = "anon";
 
 	for(n = 0; n < pcb->LayerGroups.len; n++)
-		if ((pcb->LayerGroups.grp[n].type & PCB_LYT_COPPER) && (pcb->LayerGroups.grp[n].type & PCB_LYT_INTERN))
+		if ((pcb->LayerGroups.grp[n].ltype & PCB_LYT_COPPER) && (pcb->LayerGroups.grp[n].ltype & PCB_LYT_INTERN))
 			existing_intern++;
 
 	for(n = 0; n < num_layer; n++) {
@@ -780,7 +780,7 @@
 
 		if (ly->meta.bound.type & PCB_LYT_OUTLINE) {
 			pcb_layergrp_t *grp = pcb_get_grp_new_misc(pcb);
-			grp->type = PCB_LYT_OUTLINE | PCB_LYT_INTERN;
+			grp->ltype = PCB_LYT_OUTLINE | PCB_LYT_INTERN;
 			grp->name = pcb_strdup("outline");
 			pcb_layer_create(pcb, pcb_layergrp_id(pcb, grp), ly->name);
 			continue;
@@ -884,7 +884,7 @@
 		else {
 			grp = pcb_get_grp_new_misc(pcb);
 			gid = grp - pcb->LayerGroups.grp;
-			grp->type = m->lyt;
+			grp->ltype = m->lyt;
 		}
 
 		grp->name = pcb_strdup(m->name);
@@ -905,7 +905,7 @@
 	/* check if the last known value is still accurate */
 	if ((*cache >= 0) && (*cache < pcb->LayerGroups.len)) {
 		g = &(pcb->LayerGroups.grp[*cache]);
-		if ((g->type & loc) && (g->type & typ))
+		if ((g->ltype & loc) && (g->ltype & typ))
 			return *cache;
 	}
 
@@ -1015,7 +1015,7 @@
 
 	st->cache.copper_len = 0;
 	for(n = 0; n < st->len; n++)
-		if (st->grp[n].type & PCB_LYT_COPPER)
+		if (st->grp[n].ltype & PCB_LYT_COPPER)
 			st->cache.copper[st->cache.copper_len++] = n;
 
 	st->cache.copper_valid = 1;
Index: trunk/src/layer_grp.h
===================================================================
--- trunk/src/layer_grp.h	(revision 16177)
+++ trunk/src/layer_grp.h	(revision 16178)
@@ -43,7 +43,7 @@
 	pcb_cardinal_t len;                    /* number of layer IDs in use */
 	pcb_layer_id_t lid[PCB_MAX_LAYER];     /* lid=layer ID */
 	char *name;                            /* name of the physical layer (independent of the name of the layer groups) */
-	pcb_layer_type_t type;
+	pcb_layer_type_t ltype;
 
 	unsigned valid:1;                      /* 1 if it's a new-style, valid layer group; 0 after loading old files with no layer stackup info */
 	unsigned vis:1;                        /* 1 if layer group is visible on the GUI */
Index: trunk/src/layer_vis.c
===================================================================
--- trunk/src/layer_vis.c	(revision 16177)
+++ trunk/src/layer_vis.c	(revision 16178)
@@ -281,7 +281,7 @@
 	/* do not show paste and mask by default - they are distractive */
 	for(gid = 0; gid < pcb_max_group(PCB); gid++) {
 		pcb_layergrp_t *g = &PCB->LayerGroups.grp[gid];
-		if ((g->type & PCB_LYT_MASK) || (g->type & PCB_LYT_PASTE)) {
+		if ((g->ltype & PCB_LYT_MASK) || (g->ltype & PCB_LYT_PASTE)) {
 			int n;
 			g->vis = pcb_false;
 			for(n = 0; n < g->len; n++) {
Index: trunk/src/obj_pstk.c
===================================================================
--- trunk/src/obj_pstk.c	(revision 16177)
+++ trunk/src/obj_pstk.c	(revision 16178)
@@ -413,7 +413,7 @@
 		if (grp == NULL)
 			set_ps_color(ps, ctx->is_current, ctx->shape_mask);
 		else
-			set_ps_color(ps, ctx->is_current, grp->type);
+			set_ps_color(ps, ctx->is_current, grp->ltype);
 		if (conf_core.editor.thin_draw || conf_core.editor.wireframe_draw) {
 			pcb_gui->set_line_width(pcb_draw_out.fgGC, 0);
 			pcb_pstk_draw_shape_thin(pcb_draw_out.fgGC, ps, shape);
Index: trunk/src/obj_pstk_inlines.h
===================================================================
--- trunk/src/obj_pstk_inlines.h	(revision 16177)
+++ trunk/src/obj_pstk_inlines.h	(revision 16178)
@@ -241,11 +241,11 @@
 	if ((grp == NULL) || (grp->len < 1))
 		return NULL;
 
-	if (grp->type & PCB_LYT_COPPER) {
+	if (grp->ltype & PCB_LYT_COPPER) {
 		int n, nosh;
 
 		/* blind/buried: intern layer has no shape if no hole */
-		if (grp->type & PCB_LYT_INTERN) {
+		if (grp->ltype & PCB_LYT_INTERN) {
 			/* apply internal only if that layer has drill */
 			if (!pcb_pstk_bb_drills(pcb, ps, gid, NULL))
 				return NULL;
@@ -262,7 +262,7 @@
 	}
 
 	/* normal procedure: go by group flags */
-	return pcb_pstk_shape(ps, grp->type, comb);
+	return pcb_pstk_shape(ps, grp->ltype, comb);
 }
 
 
Index: trunk/src_plugins/diag/diag.c
===================================================================
--- trunk/src_plugins/diag/diag.c	(revision 16177)
+++ trunk/src_plugins/diag/diag.c	(revision 16178)
@@ -169,7 +169,7 @@
 		printf("Per group:\n");
 		for(g = 0; g < PCB->LayerGroups.len; g++) {
 			pcb_layergrp_t *grp = &PCB->LayerGroups.grp[g];
-			printf(" Group %d: '%s' %x\n", g, grp->name, grp->type);
+			printf(" Group %d: '%s' %x\n", g, grp->name, grp->ltype);
 			for(n = 0; n < grp->len; n++) {
 				pcb_layer_t *ly = pcb_get_layer(PCB->Data, grp->lid[n]);
 				if (ly != NULL) {
Index: trunk/src_plugins/draw_csect/draw_csect.c
===================================================================
--- trunk/src_plugins/draw_csect/draw_csect.c	(revision 16177)
+++ trunk/src_plugins/draw_csect/draw_csect.c	(revision 16178)
@@ -435,7 +435,7 @@
 
 		if ((!g->valid) || (gid == drag_gid)  || (gid == drag_gid_subst))
 			continue;
-		else if (g->type & PCB_LYT_COPPER) {
+		else if (g->ltype & PCB_LYT_COPPER) {
 			last_copper_step = -last_copper_step;
 			if (last_copper_step > 0)
 				stepf = last_copper_step;
@@ -444,32 +444,32 @@
 			th = 5;
 			color = COLOR_COPPER;
 		}
-		else if (g->type & PCB_LYT_SUBSTRATE) {
+		else if (g->ltype & PCB_LYT_SUBSTRATE) {
 			stepf = stepb = 7;
 			th = 10;
 			color = COLOR_SUBSTRATE;
 		}
-		else if (g->type & PCB_LYT_SILK) {
+		else if (g->ltype & PCB_LYT_SILK) {
 			th = 5;
 			color = COLOR_SILK;
 			stepb = 3;
 		}
-		else if (g->type & PCB_LYT_MASK) {
+		else if (g->ltype & PCB_LYT_MASK) {
 			th = 5;
 			color = COLOR_MASK;
 			stepb = 9;
 		}
-		else if (g->type & PCB_LYT_PASTE) {
+		else if (g->ltype & PCB_LYT_PASTE) {
 			th = 5;
 			color = COLOR_PASTE;
 			stepf = 9;
 		}
-		else if (g->type & PCB_LYT_MISC) {
+		else if (g->ltype & PCB_LYT_MISC) {
 			th = 5;
 			color = COLOR_MISC;
 			stepf = 3;
 		}
-		else if (g->type & PCB_LYT_OUTLINE) {
+		else if (g->ltype & PCB_LYT_OUTLINE) {
 			outline_gid = gid;
 			continue;
 		}
@@ -708,11 +708,11 @@
 					pcb_layergrp_t *g;
 					g = pcb_layergrp_insert_after(PCB, gactive);
 					g->name = NULL;
-					g->type = PCB_LYT_INTERN | PCB_LYT_SUBSTRATE;
+					g->ltype = PCB_LYT_INTERN | PCB_LYT_SUBSTRATE;
 					g->valid = 1;
 					g = pcb_layergrp_insert_after(PCB, gactive);
 					g->name = pcb_strdup("Intern");
-					g->type = PCB_LYT_INTERN | PCB_LYT_COPPER;
+					g->ltype = PCB_LYT_INTERN | PCB_LYT_COPPER;
 					g->valid = 1;
 				}
 				drag_addgrp = 0;
@@ -848,14 +848,14 @@
 				continue;
 			type_gfx = "old";
 		}
-		else if (g->type & PCB_LYT_VIRTUAL) continue;
-		else if (g->type & PCB_LYT_COPPER) type_gfx = "====";
-		else if (g->type & PCB_LYT_SUBSTRATE) type_gfx = "xxxx";
-		else if (g->type & PCB_LYT_SILK) type_gfx = "silk";
-		else if (g->type & PCB_LYT_MASK) type_gfx = "mask";
-		else if (g->type & PCB_LYT_PASTE) type_gfx = "pst.";
-		else if (g->type & PCB_LYT_MISC) type_gfx = "misc";
-		else if (g->type & PCB_LYT_OUTLINE) type_gfx = "||||";
+		else if (g->ltype & PCB_LYT_VIRTUAL) continue;
+		else if (g->ltype & PCB_LYT_COPPER) type_gfx = "====";
+		else if (g->ltype & PCB_LYT_SUBSTRATE) type_gfx = "xxxx";
+		else if (g->ltype & PCB_LYT_SILK) type_gfx = "silk";
+		else if (g->ltype & PCB_LYT_MASK) type_gfx = "mask";
+		else if (g->ltype & PCB_LYT_PASTE) type_gfx = "pst.";
+		else if (g->ltype & PCB_LYT_MISC) type_gfx = "misc";
+		else if (g->ltype & PCB_LYT_OUTLINE) type_gfx = "||||";
 		else type_gfx = "????";
 
 		printf("%s {%ld} %s\n", type_gfx, gid, g->name);
Index: trunk/src_plugins/export_openems/export_openems.c
===================================================================
--- trunk/src_plugins/export_openems/export_openems.c	(revision 16177)
+++ trunk/src_plugins/export_openems/export_openems.c	(revision 16178)
@@ -249,7 +249,7 @@
 	}
 #endif
 
-	opt = (grp->type & PCB_LYT_COPPER) ? cop_opt : subs_opt;
+	opt = (grp->ltype & PCB_LYT_COPPER) ? cop_opt : subs_opt;
 	assert(opt >= 0);
 	if (is_str)
 		pcb_fprintf(ctx->f, "%s", ctx->options[opt].str_value);
@@ -270,9 +270,9 @@
 	/* linear map of copper and substrate layers */
 	for(gid = 0; gid < ctx->pcb->LayerGroups.len; gid++) {
 		pcb_layergrp_t *grp = &ctx->pcb->LayerGroups.grp[gid];
-		int iscop = (grp->type & PCB_LYT_COPPER);
+		int iscop = (grp->ltype & PCB_LYT_COPPER);
 
-		if (!(iscop) && !(grp->type & PCB_LYT_SUBSTRATE))
+		if (!(iscop) && !(grp->ltype & PCB_LYT_SUBSTRATE))
 			continue;
 		ctx->lg_ems2pcb[next] = gid;
 		ctx->lg_pcb2ems[gid] = next;
@@ -353,7 +353,7 @@
 	/* create all substrate layers using this polygon*/
 	for(n = 1; n < ctx->lg_next; n++) {
 		pcb_layergrp_t *grp = &ctx->pcb->LayerGroups.grp[ctx->lg_ems2pcb[n]];
-		if (grp->type & PCB_LYT_SUBSTRATE)
+		if (grp->ltype & PCB_LYT_SUBSTRATE)
 			fprintf(ctx->f, "CSX = AddPcbrndPoly(CSX, PCBRND, %d, outline_xy, 1);\n", n);
 	}
 
@@ -413,10 +413,10 @@
 			if (grp->len <= 0) /* group has no layers -> probably substrate */
 				continue;
 
-			if (!(grp->type & PCB_LYT_COPPER)) /* testpoint goes on copper only */
+			if (!(grp->ltype & PCB_LYT_COPPER)) /* testpoint goes on copper only */
 				continue;
 
-			if (!(grp->type & PCB_LYT_TOP) && !(grp->type & PCB_LYT_BOTTOM)) /* do not put testpoints on inner layers */
+			if (!(grp->ltype & PCB_LYT_TOP) && !(grp->ltype & PCB_LYT_BOTTOM)) /* do not put testpoints on inner layers */
 				continue;
 
 			lid = grp->lid[0];
Index: trunk/src_plugins/export_openems/mesh.c
===================================================================
--- trunk/src_plugins/export_openems/mesh.c	(revision 16177)
+++ trunk/src_plugins/export_openems/mesh.c	(revision 16178)
@@ -350,10 +350,10 @@
 
 	for(gid = 0; gid < PCB->LayerGroups.len; gid++) {
 		pcb_layergrp_t *grp = &PCB->LayerGroups.grp[gid];
-		if (grp->type & PCB_LYT_COPPER) {
+		if (grp->ltype & PCB_LYT_COPPER) {
 			y += mesh->def_copper_thick;
 		}
-		else if (grp->type & PCB_LYT_SUBSTRATE) {
+		else if (grp->ltype & PCB_LYT_SUBSTRATE) {
 			pcb_coord_t d, t = mesh->def_subs_thick;
 			double dens = (double)t/(double)lns;
 			bottom_dens = pcb_round(dens);
@@ -485,13 +485,13 @@
 
 	for(gid = 0; gid < PCB->LayerGroups.len; gid++) {
 		pcb_layergrp_t *grp = &PCB->LayerGroups.grp[gid];
-		if (grp->type & PCB_LYT_COPPER) {
+		if (grp->ltype & PCB_LYT_COPPER) {
 			y2 = y + mesh->def_copper_thick * mag / 2;
 			pcb_line_new(mesh->ui_layer_z, xr, y2, xr+PCB_MM_TO_COORD(2), y2, cpen, 0, pcb_no_flags());
 			pcb_text_new(mesh->ui_layer_z, pcb_font(PCB, 0, 0), xr+PCB_MM_TO_COORD(3), y2 - PCB_MM_TO_COORD(1), 0, 100, grp->name, pcb_no_flags());
 			y += mesh->def_copper_thick * mag;
 		}
-		else if (grp->type & PCB_LYT_SUBSTRATE) {
+		else if (grp->ltype & PCB_LYT_SUBSTRATE) {
 			y2 = y + mesh->def_subs_thick * mag;
 			pcb_line_new(mesh->ui_layer_z, xl, y, xr, y, spen, 0, pcb_no_flags());
 			pcb_line_new(mesh->ui_layer_z, xl, y2, xr, y2, spen, 0, pcb_no_flags());
Index: trunk/src_plugins/io_autotrax/read.c
===================================================================
--- trunk/src_plugins/io_autotrax/read.c	(revision 16177)
+++ trunk/src_plugins/io_autotrax/read.c	(revision 16178)
@@ -820,7 +820,7 @@
 
 	g = pcb_get_grp_new_intern(st->pcb, -1);
 	g->name = pcb_strdup("outline"); /* equivalent to keepout = layer 12 in autotrax */
-	g->type = PCB_LYT_OUTLINE; /* and includes cutouts */
+	g->ltype = PCB_LYT_OUTLINE; /* and includes cutouts */
 	st->protel_to_stackup[12] = autotrax_reg_layer(st, "outline", PCB_LYT_OUTLINE);
 
 	pcb_layergrp_inhibit_dec();
Index: trunk/src_plugins/io_autotrax/write.c
===================================================================
--- trunk/src_plugins/io_autotrax/write.c	(revision 16177)
+++ trunk/src_plugins/io_autotrax/write.c	(revision 16178)
@@ -110,16 +110,16 @@
 		pcb_layergrp_t *grp = &ctx->pcb->LayerGroups.grp[n];
 		int al;
 
-		if ((grp->type & PCB_LYT_SUBSTRATE) || (grp->type & PCB_LYT_VIRTUAL) || (grp->type & PCB_LYT_PASTE) || (grp->type & PCB_LYT_MASK))
+		if ((grp->ltype & PCB_LYT_SUBSTRATE) || (grp->ltype & PCB_LYT_VIRTUAL) || (grp->ltype & PCB_LYT_PASTE) || (grp->ltype & PCB_LYT_MASK))
 			continue;
 
-		al = wrax_lyt2id(ctx, grp->type);
+		al = wrax_lyt2id(ctx, grp->ltype);
 		if (al == 0) {
 			wrax_map_layer_error(ctx, grp, "Unable to map pcb-rnd layer group to autotrax layer", "change layer type");
 			continue;
 		}
 
-		if (grp->type & PCB_LYT_INTERN) {
+		if (grp->ltype & PCB_LYT_INTERN) {
 			/* intern copper: find the first free slot */
 			while((layer_map[al+intcnt].lyt & PCB_LYT_INTERN) && (ctx->id2grp[al+intcnt] != NULL)) intcnt++;
 			al += intcnt;
Index: trunk/src_plugins/io_hyp/write.c
===================================================================
--- trunk/src_plugins/io_hyp/write.c	(revision 16177)
+++ trunk/src_plugins/io_hyp/write.c	(revision 16178)
@@ -251,7 +251,7 @@
 			loc = (shp->layer_mask & PCB_LYT_ANYWHERE);
 			for(l = 0; l < wr->pcb->LayerGroups.len; l++) {
 				pcb_layergrp_t *lg = &wr->pcb->LayerGroups.grp[l];
-				pcb_layer_type_t lyt = lg->type;
+				pcb_layer_type_t lyt = lg->ltype;
 				if ((lyt & PCB_LYT_COPPER) && (lyt & loc))
 					hyp_pstk_shape(wr, hyp_grp_name(wr, lg, NULL), shp);
 			}
@@ -396,14 +396,14 @@
 		pcb_layergrp_t *grp = &wr->pcb->LayerGroups.grp[n];
 		const char *name = grp->name;
 
-		if (grp->type & PCB_LYT_COPPER) {
+		if (grp->ltype & PCB_LYT_COPPER) {
 			pcb_fprintf(wr->f, "  (SIGNAL T=0.003500 L=%[4])\n", hyp_grp_name(wr, grp, name));
-			if (grp->type & PCB_LYT_TOP)
+			if (grp->ltype & PCB_LYT_TOP)
 				wr->ln_top = name;
-			else if (grp->type & PCB_LYT_BOTTOM)
+			else if (grp->ltype & PCB_LYT_BOTTOM)
 				wr->ln_bottom = name;
 		}
-		else if (grp->type & PCB_LYT_SUBSTRATE) {
+		else if (grp->ltype & PCB_LYT_SUBSTRATE) {
 			char tmp[128];
 			if (name == NULL) {
 				sprintf(tmp, "dielectric layer %d", n);
Index: trunk/src_plugins/io_kicad/write.c
===================================================================
--- trunk/src_plugins/io_kicad/write.c	(revision 16177)
+++ trunk/src_plugins/io_kicad/write.c	(revision 16178)
@@ -187,7 +187,7 @@
 
 	for(n = 0; n < ctx->pcb->LayerGroups.len; n++) {
 		pcb_layergrp_t *grp = &ctx->pcb->LayerGroups.grp[n];
-		if ((mapped[n] == 0) && !(grp->type & PCB_LYT_SUBSTRATE))
+		if ((mapped[n] == 0) && !(grp->ltype & PCB_LYT_SUBSTRATE))
 			pcb_io_incompat_save(ctx->pcb->Data, NULL, "Failed to map layer for export - layer omitted", grp->name);
 		else if (mapped[n] > 1)
 			pcb_io_incompat_save(ctx->pcb->Data, NULL, "Mapped layer for export multiple times", grp->name);
Index: trunk/src_plugins/io_lihata/read.c
===================================================================
--- trunk/src_plugins/io_lihata/read.c	(revision 16177)
+++ trunk/src_plugins/io_lihata/read.c	(revision 16178)
@@ -1226,7 +1226,7 @@
 		}
 		else
 			g->name = pcb_strdup(name->data.text.value);
-		parse_layer_type(&g->type, lht_dom_hash_get(grp, "type"), g->name);
+		parse_layer_type(&g->ltype, lht_dom_hash_get(grp, "type"), g->name);
 
 		/* load layers */
 		layers = lht_dom_hash_get(grp, "layers");
Index: trunk/src_plugins/io_lihata/write.c
===================================================================
--- trunk/src_plugins/io_lihata/write.c	(revision 16177)
+++ trunk/src_plugins/io_lihata/write.c	(revision 16178)
@@ -749,7 +749,7 @@
 			lht_dom_list_append(layers, build_textf("", "%ld", g->lid[i]));
 
 		lht_dom_hash_put(grp, flags = lht_dom_node_alloc(LHT_HASH, "type"));
-		pcb_layer_type_map(g->type, flags, build_layer_stack_flag);
+		pcb_layer_type_map(g->ltype, flags, build_layer_stack_flag);
 	}
 
 	return lstk;
Index: trunk/src_plugins/lib_gtk_common/dlg_propedit.c
===================================================================
--- trunk/src_plugins/lib_gtk_common/dlg_propedit.c	(revision 16177)
+++ trunk/src_plugins/lib_gtk_common/dlg_propedit.c	(revision 16178)
@@ -320,7 +320,7 @@
 	memcpy(&preview_pcb.LayerGroups, &old_pcb->LayerGroups, sizeof(old_pcb->LayerGroups));
 	preview_pcb.Data->LayerN = 1;
 	preview_pcb.Data->Layer[0].meta.real.grp = 0;
-	preview_pcb.LayerGroups.grp[0].type = PCB_LYT_COPPER | PCB_LYT_TOP;
+	preview_pcb.LayerGroups.grp[0].ltype = PCB_LYT_COPPER | PCB_LYT_TOP;
 	preview_pcb.LayerGroups.grp[0].lid[0] = 0;
 	preview_pcb.LayerGroups.grp[0].len = 1;
 	preview_pcb.LayerGroups.len = 1;
Index: trunk/src_plugins/lib_gtk_common/wt_layersel.c
===================================================================
--- trunk/src_plugins/lib_gtk_common/wt_layersel.c	(revision 16177)
+++ trunk/src_plugins/lib_gtk_common/wt_layersel.c	(revision 16178)
@@ -415,7 +415,7 @@
 
 static const char * const grp_color(pcb_layergrp_t *g)
 {
-	hardwired_colors(g->type);
+	hardwired_colors(g->ltype);
 	/* normal mechanism: first layer's color or yellow */
 	if (g->len == 0) return "#ffff00";
 	return lyr_color(g->lid[0]);
@@ -576,7 +576,7 @@
 
 	for(gid = 0; gid < pcb_max_group(PCB); gid++) {
 		pcb_layergrp_t *g = &PCB->LayerGroups.grp[gid];
-		if (g->type & PCB_LYT_SUBSTRATE)
+		if (g->ltype & PCB_LYT_SUBSTRATE)
 			continue;
 		gtk_box_pack_start(GTK_BOX(ls->grp_box), build_group_real(ls, &ls->grp[gid], g), FALSE, FALSE, 0);
 	}
Index: trunk/src_plugins/lib_hid_common/layer_menu.c
===================================================================
--- trunk/src_plugins/lib_hid_common/layer_menu.c	(revision 16177)
+++ trunk/src_plugins/lib_hid_common/layer_menu.c	(revision 16178)
@@ -115,7 +115,7 @@
 		pcb_layergrp_t *g = &PCB->LayerGroups.grp[gid];
 		int n;
 
-		if (g->type & PCB_LYT_SUBSTRATE)
+		if (g->ltype & PCB_LYT_SUBSTRATE)
 			continue;
 
 		for(n = g->len-1; n >= 0; n--) {