Index: trunk/src/layer.c =================================================================== --- trunk/src/layer.c (revision 19202) +++ trunk/src/layer.c (revision 19203) @@ -83,7 +83,6 @@ { PCB_LYT_SILK, 2, "silk" }, { PCB_LYT_MASK, 2, "mask" }, { PCB_LYT_PASTE, 2, "paste" }, - { PCB_LYT_OUTLINE, 2, "outline" }, { PCB_LYT_BOUNDARY,2, "boundary" }, { PCB_LYT_RAT, 2, "rat" }, { PCB_LYT_INVIS, 2, "invis" }, Index: trunk/src/layer.h =================================================================== --- trunk/src/layer.h (revision 19202) +++ trunk/src/layer.h (revision 19203) @@ -48,7 +48,6 @@ PCB_LYT_SILK = 0x00000200, /* silk objects */ PCB_LYT_MASK = 0x00000400, /* solder mask */ PCB_LYT_PASTE = 0x00000800, /* paste */ - PCB_LYT_OUTLINE = 0x00001000, /* outline (contour of the board) */ PCB_LYT_RAT = 0x00002000, /* (virtual) rats nest (one, not in the stackup) */ PCB_LYT_INVIS = 0x00004000, /* (virtual) layer is invisible (one, not in the stackup) */ PCB_LYT_BOUNDARY = 0x00008000, /* physical boundaries of the board (inner and outer): route, cuts, slots, drills */ @@ -99,15 +98,15 @@ #define PCB_LAYER_IS_DRILL(lyt, purpi) (((lyt) & PCB_LYT_VIRTUAL) && (((purpi) == F_pdrill) || ((purpi) == F_udrill))) /* Route must be on a mech or boundary layer */ -#define PCB_LAYER_IS_UROUTE(lyt, purpi) ((((lyt) & (PCB_LYT_BOUNDARY | PCB_LYT_MECH)) && ((((purpi) == F_uroute)))) || ((lyt) & PCB_LYT_OUTLINE)) -#define PCB_LAYER_IS_PROUTE(lyt, purpi) ((((lyt) & (PCB_LYT_BOUNDARY | PCB_LYT_MECH)) && (((purpi) == F_proute)))) -#define PCB_LAYER_IS_ROUTE(lyt, purpi) ((((lyt) & (PCB_LYT_BOUNDARY | PCB_LYT_MECH)) && (((purpi) == F_proute) || ((purpi) == F_uroute))) || ((lyt) & PCB_LYT_OUTLINE)) +#define PCB_LAYER_IS_UROUTE(lyt, purpi) (((lyt) & (PCB_LYT_BOUNDARY | PCB_LYT_MECH)) && ((((purpi) == F_uroute)))) +#define PCB_LAYER_IS_PROUTE(lyt, purpi) (((lyt) & (PCB_LYT_BOUNDARY | PCB_LYT_MECH)) && (((purpi) == F_proute))) +#define PCB_LAYER_IS_ROUTE(lyt, purpi) (((lyt) & (PCB_LYT_BOUNDARY | PCB_LYT_MECH)) && (((purpi) == F_proute) || ((purpi) == F_uroute))) /* Outline is a route in a boundary group; outline in this sense means the "perimeter of the board", but could include largish internal cutout - the user needs to be explicit about this. Mech layers are NOT included, that's the difference compared to routed layers */ -#define PCB_LAYER_IS_OUTLINE(lyt, purpi) ((((lyt) & PCB_LYT_BOUNDARY) && (((purpi) == F_proute) || ((purpi) == F_uroute))) || ((lyt) & PCB_LYT_OUTLINE)) +#define PCB_LAYER_IS_OUTLINE(lyt, purpi) (((lyt) & PCB_LYT_BOUNDARY) && (((purpi) == F_proute) || ((purpi) == F_uroute))) #include "globalconst.h" #include "global_typedefs.h" Index: trunk/src_plugins/dialogs/dlg_layer_binding.c =================================================================== --- trunk/src_plugins/dialogs/dlg_layer_binding.c (revision 19202) +++ trunk/src_plugins/dialogs/dlg_layer_binding.c (revision 19203) @@ -32,7 +32,7 @@ #include "search.h" static const char *lb_comp[] = { "+manual", "-manual", "+auto", "-auto", NULL }; -static const char *lb_types[] = { "UNKNOWN", "paste", "mask", "silk", "copper", "outline", "mech", "doc", "virtual", NULL }; +static const char *lb_types[] = { "UNKNOWN", "paste", "mask", "silk", "copper", "boundary", "mech", "doc", "virtual", NULL }; static const char *lb_side[] = { "top", "bottom", NULL }; typedef struct { @@ -55,7 +55,7 @@ else if (type & PCB_LYT_MASK) return 2; else if (type & PCB_LYT_SILK) return 3; else if (type & PCB_LYT_COPPER) return 4; - else if (type & PCB_LYT_OUTLINE) return 5; + else if (type & PCB_LYT_BOUNDARY) return 5; else if (type & PCB_LYT_MECH) return 6; else if (type & PCB_LYT_DOC) return 7; else if (type & PCB_LYT_VIRTUAL) return 8; @@ -78,7 +78,7 @@ case 2: *type |= PCB_LYT_MASK; break; case 3: *type |= PCB_LYT_SILK; break; case 4: *type |= PCB_LYT_COPPER; break; - case 5: *type |= PCB_LYT_OUTLINE; break; + case 5: *type |= PCB_LYT_BOUNDARY; break; case 6: *type |= PCB_LYT_MECH; break; case 7: *type |= PCB_LYT_DOC; break; case 8: *type |= PCB_LYT_VIRTUAL; break; @@ -123,7 +123,7 @@ int ofs; /* disable comp for copper and outline */ - enable = !(layer->meta.bound.type & PCB_LYT_COPPER) && !(layer->meta.bound.type & PCB_LYT_OUTLINE); + enable = !(layer->meta.bound.type & PCB_LYT_COPPER) && !(layer->meta.bound.type & PCB_LYT_BOUNDARY); pcb_gui->attr_dlg_widget_state(hid_ctx, w->comp, enable); if (!enable) layer->comb = 0; /* copper and outline must be +manual */ @@ -184,7 +184,7 @@ get_ly_type(ctx->attrs[w->type].default_val.int_value, ctx->attrs[w->side].default_val.int_value, ctx->attrs[w->offs].default_val.int_value, &layer->meta.bound.type, &layer->meta.bound.stack_offs); /* enforce some sanity rules */ - if (layer->meta.bound.type & PCB_LYT_OUTLINE) { + if (layer->meta.bound.type & PCB_LYT_BOUNDARY) { /* outline must be positive global */ layer->comb = 0; layer->meta.bound.type &= ~PCB_LYT_ANYWHERE; Index: trunk/src_plugins/draw_csect/draw_csect.c =================================================================== --- trunk/src_plugins/draw_csect/draw_csect.c (revision 19202) +++ trunk/src_plugins/draw_csect/draw_csect.c (revision 19203) @@ -470,7 +470,7 @@ stepf = 3; } #warning layer TODO: handle multiple outline layers - else if ((g->ltype & PCB_LYT_BOUNDARY) || (g->ltype & PCB_LYT_OUTLINE)) { + else if (g->ltype & PCB_LYT_BOUNDARY) { outline_gid = gid; continue; } Index: trunk/src_plugins/export_gerber/gerber.c =================================================================== --- trunk/src_plugins/export_gerber/gerber.c (revision 19202) +++ trunk/src_plugins/export_gerber/gerber.c (revision 19203) @@ -885,7 +885,6 @@ if (want_outline && !(PCB_LAYER_IS_ROUTE(flags, purpi))) { if (has_outline) { - pcb_draw_groups(PCB, PCB_LYT_OUTLINE, -1, NULL, ®ion, "#000000", 0, 0, 0); pcb_draw_groups(PCB, PCB_LYT_BOUNDARY, F_proute, NULL, ®ion, "#000000", PCB_LYT_MECH, 0, 0); pcb_draw_groups(PCB, PCB_LYT_BOUNDARY, F_uroute, NULL, ®ion, "#000000", PCB_LYT_MECH, 0, 0); } Index: trunk/src_plugins/export_ps/ps.c =================================================================== --- trunk/src_plugins/export_ps/ps.c (revision 19202) +++ trunk/src_plugins/export_ps/ps.c (revision 19203) @@ -667,8 +667,6 @@ pcb_layer_listp(PCB, PCB_LYT_BOUNDARY, &lid, 1, F_uroute, NULL); if (lid == -1) pcb_layer_listp(PCB, PCB_LYT_BOUNDARY, &lid, 1, F_proute, NULL); - if (lid == -1) - pcb_layer_listp(PCB, PCB_LYT_OUTLINE, &lid, 1, -1, NULL); global.has_outline = (lid >= 0); memcpy(saved_layer_stack, pcb_layer_stack, sizeof(pcb_layer_stack)); @@ -1003,7 +1001,6 @@ !(PCB_LAYER_IS_ROUTE(flags, purpi))) { int save_drill = global.is_drill; global.is_drill = 0; - pcb_draw_groups(PCB, PCB_LYT_OUTLINE, -1, NULL, &global.exps.view, "#000000", 0, 0, 0); pcb_draw_groups(PCB, PCB_LYT_BOUNDARY, F_proute, NULL, &global.exps.view, "#000000", PCB_LYT_MECH, 0, 0); pcb_draw_groups(PCB, PCB_LYT_BOUNDARY, F_uroute, NULL, &global.exps.view, "#000000", PCB_LYT_MECH, 0, 0); global.is_drill = save_drill; Index: trunk/src_plugins/io_lihata/write.c =================================================================== --- trunk/src_plugins/io_lihata/write.c (revision 19202) +++ trunk/src_plugins/io_lihata/write.c (revision 19203) @@ -871,9 +871,12 @@ lyt = g->ltype; if (wrver < 6) { - if (g->purpose != NULL) + int is_outline = (PCB_LAYER_IS_OUTLINE(g->ltype, g->purpi)); + + if ((!is_outline) && (g->purpose != NULL)) pcb_io_incompat_save(pcb->Data, (pcb_any_obj_t *)g, "Can not save layer group purpose in lihata formats below version 6.", "Either save in lihata v6 - or accept that these layers will change type in the file"); - if (PCB_LAYER_IS_OUTLINE(g->ltype, g->purpi)) { + + if (is_outline) { lht_dom_hash_put(grp, flags = lht_dom_node_alloc(LHT_HASH, "type")); pcb_layer_type_map(lyt & (~PCB_LYT_ANYTHING), flags, build_layer_stack_flag); lht_dom_hash_put(flags, build_text("outline", "1")); Index: trunk/src_plugins/lib_gtk_common/dlg_propedit.c =================================================================== --- trunk/src_plugins/lib_gtk_common/dlg_propedit.c (revision 19202) +++ trunk/src_plugins/lib_gtk_common/dlg_propedit.c (revision 19203) @@ -384,7 +384,7 @@ pcb_board_t *old_pcb; old_pcb = PCB; PCB = &preview_pcb; - pcb_draw_layer(&(PCB->Data->Layer[0]), &e->view); + pcb_draw_layer(&(PCB->Data->Layer[0]), &e->view, NULL); pcb_draw_ppv(0, &e->view); PCB = old_pcb; }