Index: trunk/src/draw.c
===================================================================
--- trunk/src/draw.c	(revision 19397)
+++ trunk/src/draw.c	(revision 19398)
@@ -463,56 +463,45 @@
 static void pcb_draw_pstks(pcb_draw_info_t *info, pcb_layergrp_id_t group, int is_current, pcb_layer_combining_t comb)
 {
 	pcb_layergrp_t *g = PCB->LayerGroups.grp + group;
-	pcb_pstk_draw_t ctx;
-	ctx.pcb = PCB;
-	ctx.gid = group;
-	ctx.is_current = is_current;
-	ctx.comb = comb;
+
+	info->objcb.pstk.gid = group;
+	info->objcb.pstk.is_current = is_current;
+	info->objcb.pstk.comb = comb;
 	if (g->len > 0)
-		ctx.layer1 = pcb_get_layer(PCB->Data, g->lid[0]);
+		info->objcb.pstk.layer1 = pcb_get_layer(info->pcb->Data, g->lid[0]);
 	else
-		ctx.layer1 = NULL;
-	pcb_r_search(PCB->Data->padstack_tree, info->drawn_area, NULL, pcb_pstk_draw_callback, &ctx, NULL);
+		info->objcb.pstk.layer1 = NULL;
+	pcb_r_search(info->pcb->Data->padstack_tree, info->drawn_area, NULL, pcb_pstk_draw_callback, info, NULL);
 }
 
 static void pcb_draw_pstk_marks(pcb_draw_info_t *info)
 {
-	pcb_pstk_draw_t ctx;
-	ctx.pcb = PCB;
-	pcb_r_search(PCB->Data->padstack_tree, info->drawn_area, NULL, pcb_pstk_draw_mark_callback, &ctx, NULL);
+	pcb_r_search(PCB->Data->padstack_tree, info->drawn_area, NULL, pcb_pstk_draw_mark_callback, info, NULL);
 }
 
 static void pcb_draw_pstk_labels(pcb_draw_info_t *info)
 {
-	pcb_pstk_draw_t ctx;
-	ctx.pcb = PCB;
-	pcb_r_search(PCB->Data->padstack_tree, info->drawn_area, NULL, pcb_pstk_draw_label_callback, &ctx, NULL);
+	pcb_r_search(PCB->Data->padstack_tree, info->drawn_area, NULL, pcb_pstk_draw_label_callback, info, NULL);
 }
 
 static void pcb_draw_pstk_holes(pcb_draw_info_t *info, pcb_layergrp_id_t group, pcb_pstk_draw_hole_t holetype)
 {
-	pcb_pstk_draw_t ctx;
-
 	if (!PCB->hole_on)
 		return;
 
-	ctx.pcb = PCB;
-	ctx.gid = group;
-	ctx.holetype = holetype;
-	pcb_r_search(PCB->Data->padstack_tree, info->drawn_area, NULL, pcb_pstk_draw_hole_callback, &ctx, NULL);
+	info->objcb.pstk.gid = group;
+	info->objcb.pstk.holetype = holetype;
+	pcb_r_search(PCB->Data->padstack_tree, info->drawn_area, NULL, pcb_pstk_draw_hole_callback, info, NULL);
 }
 
 static void pcb_draw_pstk_slots(pcb_draw_info_t *info, pcb_layergrp_id_t group, pcb_pstk_draw_hole_t holetype)
 {
-	pcb_pstk_draw_t ctx;
-
 	if (!PCB->hole_on)
 		return;
 
-	ctx.pcb = PCB;
-	ctx.gid = group;
-	ctx.holetype = holetype;
-	pcb_r_search(PCB->Data->padstack_tree, info->drawn_area, NULL, pcb_pstk_draw_slot_callback, &ctx, NULL);
+	info->objcb.pstk.gid = group;
+	info->objcb.pstk.holetype = holetype;
+	pcb_r_search(PCB->Data->padstack_tree, info->drawn_area, NULL, pcb_pstk_draw_slot_callback, info, NULL);
 }
 
 /* ---------------------------------------------------------------------------
Index: trunk/src/draw.h
===================================================================
--- trunk/src/draw.h	(revision 19397)
+++ trunk/src/draw.h	(revision 19398)
@@ -41,6 +41,12 @@
 
 extern pcb_output_t pcb_draw_out;
 
+typedef enum {
+	PCB_PHOLE_PLATED = 1,
+	PCB_PHOLE_UNPLATED = 2,
+	PCB_PHOLE_BB = 4
+} pcb_pstk_draw_hole_t;
+
 /* Some low level draw callback depend on this in their void *cl */
 typedef struct pcb_draw_info_s {
 	const pcb_board_t *pcb;
@@ -49,6 +55,18 @@
 	pcb_xform_t *xform;                    /* the final transformation applied on objects */
 
 	const pcb_layer_t *layer;
+
+	union { /* fields used for specific object callbacks */
+		struct {
+			pcb_layergrp_id_t gid;
+			int is_current;
+			pcb_pstk_draw_hole_t holetype;
+			pcb_layer_combining_t comb;
+			pcb_layer_t *layer1; /* first (real) layer in the target group */
+
+			pcb_layer_type_t shape_mask; /* when gid is invalid, use this for the shapes */
+		} pstk;
+	} objcb;
 } pcb_draw_info_t;
 
 /* Temporarily inhibid drawing if this is non-zero. A function that calls a
Index: trunk/src/obj_pstk.c
===================================================================
--- trunk/src/obj_pstk.c	(revision 19397)
+++ trunk/src/obj_pstk.c	(revision 19398)
@@ -402,7 +402,7 @@
 
 pcb_r_dir_t pcb_pstk_draw_callback(const pcb_box_t *b, void *cl)
 {
-	pcb_pstk_draw_t *ctx = cl;
+	pcb_draw_info_t *info = cl;
 	pcb_pstk_t *ps = (pcb_pstk_t *)b;
 	pcb_pstk_shape_t *shape;
 	pcb_layergrp_t *grp = NULL;
@@ -413,20 +413,20 @@
 	if (!PCB->SubcPartsOn && pcb_gobj_parent_subc(ps->parent_type, &ps->parent))
 		return PCB_R_DIR_NOT_FOUND;
 
-	if (ctx->gid < 0) {
-		if (ctx->shape_mask != 0)
-			shape = pcb_pstk_shape(ps, ctx->shape_mask, ctx->comb);
+	if (info->objcb.pstk.gid < 0) {
+		if (info->objcb.pstk.shape_mask != 0)
+			shape = pcb_pstk_shape(ps, info->objcb.pstk.shape_mask, info->objcb.pstk.comb);
 		else
 			return PCB_R_DIR_NOT_FOUND;
 	}
 	else
-		shape = pcb_pstk_shape_gid(ctx->pcb, ps, ctx->gid, ctx->comb, &grp);
+		shape = pcb_pstk_shape_gid(info->pcb, ps, info->objcb.pstk.gid, info->objcb.pstk.comb, &grp);
 
 	if (shape != NULL) {
 		if (grp == NULL)
-			set_ps_color(ps, ctx->is_current, ctx->shape_mask, ctx->layer1);
+			set_ps_color(ps, info->objcb.pstk.is_current, info->objcb.pstk.shape_mask, info->objcb.pstk.layer1);
 		else
-			set_ps_color(ps, ctx->is_current, grp->ltype, ctx->layer1);
+			set_ps_color(ps, info->objcb.pstk.is_current, grp->ltype, info->objcb.pstk.layer1);
 		if (conf_core.editor.thin_draw || conf_core.editor.wireframe_draw) {
 			pcb_hid_set_line_width(pcb_draw_out.fgGC, 0);
 			pcb_pstk_draw_shape_thin(pcb_draw_out.fgGC, ps, shape);
@@ -481,17 +481,17 @@
 
 pcb_r_dir_t pcb_pstk_draw_hole_callback(const pcb_box_t *b, void *cl)
 {
-	pcb_pstk_draw_t *ctx = cl;
+	pcb_draw_info_t *info = cl;
 	pcb_pstk_t *ps = (pcb_pstk_t *)b;
 	pcb_pstk_proto_t *proto;
 
 	/* hide subc parts if requested */
-	if (!PCB->SubcPartsOn && pcb_gobj_parent_subc(ps->parent_type, &ps->parent))
+	if (!info->pcb->SubcPartsOn && pcb_gobj_parent_subc(ps->parent_type, &ps->parent))
 		return PCB_R_DIR_NOT_FOUND;
 
 	/* no hole in this layer group */
-	if (ctx->gid >= 0) {
-		if (!pcb_pstk_bb_drills(ctx->pcb, ps, ctx->gid, &proto))
+	if (info->objcb.pstk.gid >= 0) {
+		if (!pcb_pstk_bb_drills(info->pcb, ps, info->objcb.pstk.gid, &proto))
 			return PCB_R_DIR_FOUND_CONTINUE;
 	}
 	else
@@ -502,15 +502,15 @@
 		return PCB_R_DIR_NOT_FOUND;
 
 	/* hole is plated, but the caller doesn't want plated holes */
-	if (proto->hplated && (!(ctx->holetype & PCB_PHOLE_PLATED)))
+	if (proto->hplated && (!(info->objcb.pstk.holetype & PCB_PHOLE_PLATED)))
 		return PCB_R_DIR_NOT_FOUND;
 
 	/* hole is unplated, but the caller doesn't want unplated holes */
-	if (!proto->hplated && (!(ctx->holetype & PCB_PHOLE_UNPLATED)))
+	if (!proto->hplated && (!(info->objcb.pstk.holetype & PCB_PHOLE_UNPLATED)))
 		return PCB_R_DIR_NOT_FOUND;
 
 	/* BBvia, but the caller doesn't want BBvias */
-	if (((proto->htop != 0) || (proto->hbottom != 0)) && (!(ctx->holetype & PCB_PHOLE_BB)))
+	if (((proto->htop != 0) || (proto->hbottom != 0)) && (!(info->objcb.pstk.holetype & PCB_PHOLE_BB)))
 		return PCB_R_DIR_NOT_FOUND;
 
 	/* actual hole */
@@ -533,18 +533,18 @@
 
 pcb_r_dir_t pcb_pstk_draw_slot_callback(const pcb_box_t *b, void *cl)
 {
-	pcb_pstk_draw_t *ctx = cl;
+	pcb_draw_info_t *info = cl;
 	pcb_pstk_t *ps = (pcb_pstk_t *)b;
 	pcb_pstk_proto_t *proto;
 	pcb_pstk_shape_t *shape;
 
 	/* hide subc parts if requested */
-	if (!PCB->SubcPartsOn && pcb_gobj_parent_subc(ps->parent_type, &ps->parent))
+	if (!info->pcb->SubcPartsOn && pcb_gobj_parent_subc(ps->parent_type, &ps->parent))
 		return PCB_R_DIR_NOT_FOUND;
 
 	/* no slot in this layer group */
-	if (ctx->gid >= 0) {
-		if (!pcb_pstk_bb_drills(ctx->pcb, ps, ctx->gid, &proto))
+	if (info->objcb.pstk.gid >= 0) {
+		if (!pcb_pstk_bb_drills(info->pcb, ps, info->objcb.pstk.gid, &proto))
 			return PCB_R_DIR_FOUND_CONTINUE;
 	}
 	else
@@ -555,15 +555,15 @@
 		return PCB_R_DIR_NOT_FOUND;
 
 	/* hole is plated, but the caller doesn't want plated holes */
-	if (proto->hplated && (!(ctx->holetype & PCB_PHOLE_PLATED)))
+	if (proto->hplated && (!(info->objcb.pstk.holetype & PCB_PHOLE_PLATED)))
 		return PCB_R_DIR_NOT_FOUND;
 
 	/* hole is unplated, but the caller doesn't want unplated holes */
-	if (!proto->hplated && (!(ctx->holetype & PCB_PHOLE_UNPLATED)))
+	if (!proto->hplated && (!(info->objcb.pstk.holetype & PCB_PHOLE_UNPLATED)))
 		return PCB_R_DIR_NOT_FOUND;
 
 	/* BBslot, but the caller doesn't want BBslot */
-	if (((proto->htop != 0) || (proto->hbottom != 0)) && (!(ctx->holetype & PCB_PHOLE_BB)))
+	if (((proto->htop != 0) || (proto->hbottom != 0)) && (!(info->objcb.pstk.holetype & PCB_PHOLE_BB)))
 		return PCB_R_DIR_NOT_FOUND;
 
 	/* actual slot */
Index: trunk/src/obj_pstk_draw.h
===================================================================
--- trunk/src/obj_pstk_draw.h	(revision 19397)
+++ trunk/src/obj_pstk_draw.h	(revision 19398)
@@ -35,23 +35,6 @@
 #include "board.h"
 #include "layer_grp.h"
 
-typedef enum {
-	PCB_PHOLE_PLATED = 1,
-	PCB_PHOLE_UNPLATED = 2,
-	PCB_PHOLE_BB = 4
-} pcb_pstk_draw_hole_t;
-
-typedef struct {
-	pcb_board_t *pcb;
-	pcb_layergrp_id_t gid;
-	int is_current;
-	pcb_pstk_draw_hole_t holetype;
-	pcb_layer_combining_t comb;
-	pcb_layer_t *layer1; /* first (real) layer in the target group */
-
-	pcb_layer_type_t shape_mask; /* when gid is invalid, use this for the shapes */
-} pcb_pstk_draw_t;
-
 pcb_r_dir_t pcb_pstk_draw_callback(const pcb_box_t *b, void *cl);
 pcb_r_dir_t pcb_pstk_draw_hole_callback(const pcb_box_t *b, void *cl);
 pcb_r_dir_t pcb_pstk_draw_slot_callback(const pcb_box_t *b, void *cl);
Index: trunk/src/obj_subc.c
===================================================================
--- trunk/src/obj_subc.c	(revision 19397)
+++ trunk/src/obj_subc.c	(revision 19398)
@@ -1666,7 +1666,7 @@
 void pcb_subc_draw_preview(const pcb_subc_t *sc, const pcb_box_t *drawn_area)
 {
 	int n;
-	pcb_pstk_draw_t ctx;
+	pcb_draw_info_t info;
 	pcb_rtree_it_t it;
 	pcb_any_obj_t *o;
 
@@ -1678,18 +1678,21 @@
 	}
 
 	/* draw padstacks */
-	ctx.pcb = NULL;
-	ctx.gid = -1;
-	ctx.is_current = 1;
-	ctx.comb = 0;
-	ctx.shape_mask = PCB_LYT_COPPER | PCB_LYT_TOP;
-	ctx.holetype = PCB_PHOLE_UNPLATED | PCB_PHOLE_PLATED;
+	info.pcb = NULL;
+	info.drawn_area = drawn_area;
+	info.xform_caller = info.xform = NULL;
+	info.layer = NULL;
+	info.objcb.pstk.gid = -1;
+	info.objcb.pstk.is_current = 1;
+	info.objcb.pstk.comb = 0;
+	info.objcb.pstk.shape_mask = PCB_LYT_COPPER | PCB_LYT_TOP;
+	info.objcb.pstk.holetype = PCB_PHOLE_UNPLATED | PCB_PHOLE_PLATED;
 
 	for(o = pcb_rtree_first(&it, sc->data->padstack_tree, (pcb_rtree_box_t *)drawn_area); o != NULL; o = pcb_rtree_next(&it)) {
 		if (pcb_obj_is_under(o, sc->data)) {
-			pcb_pstk_draw_callback((pcb_box_t *)o, &ctx);
+			pcb_pstk_draw_callback((pcb_box_t *)o, &info);
 			if (PCB->hole_on)
-				pcb_pstk_draw_hole_callback((pcb_box_t *)o, &ctx);
+				pcb_pstk_draw_hole_callback((pcb_box_t *)o, &info);
 		}
 	}
 
@@ -1703,7 +1706,7 @@
 	/* padstack mark goes on top */
 	for(o = pcb_rtree_first(&it, sc->data->padstack_tree, (pcb_rtree_box_t *)drawn_area); o != NULL; o = pcb_rtree_next(&it))
 		if (pcb_obj_is_under(o, sc->data))
-			pcb_pstk_draw_mark_callback((pcb_box_t *)o, &ctx);
+			pcb_pstk_draw_mark_callback((pcb_box_t *)o, &info);
 }