Index: trunk/doc/user/09_appendix/action_details.html =================================================================== --- trunk/doc/user/09_appendix/action_details.html (revision 20600) +++ trunk/doc/user/09_appendix/action_details.html (revision 20601) @@ -88,6 +88,14 @@
The join flag determines whether a line or arc, drawn to intersect a polygon, electrically connects to the polygon or not. When joined, the line/arc is simply drawn over the polygon, making an electrical connection. When not joined, a gap is drawn between the line and the polygon, insulating them from each other. +
+This can be especially useful for annotating pin names from a schematic to the layout without requiring knowledge of the pcb file format. +
+
+Example: ChangePinName(U3, 7, VCC)
+
+
For lines and arcs, this changes the width. For padstacks, this changes the shape size (but does not touch the hole diameter). For texts, this changes the scaling factor. For subcircuits, this changes the width of the silk layer lines and arcs for this subcircuit (TODO: is this still true?). Index: trunk/doc/user/09_appendix/action_src/changepinname.html =================================================================== --- trunk/doc/user/09_appendix/action_src/changepinname.html (nonexistent) +++ trunk/doc/user/09_appendix/action_src/changepinname.html (revision 20601) @@ -0,0 +1,5 @@ +This can be especially useful for annotating pin names from a +schematic to the layout without requiring knowledge of the pcb file +format. +
+
"
+ next
+ }
+
/^