Index: 7805/7805.sch =================================================================== --- 7805/7805.sch (revision 24785) +++ 7805/7805.sch (revision 24786) @@ -8,31 +8,20 @@ T 23400 58800 5 10 1 1 0 0 1 footprint=TO220 } -C 21100 57200 1 0 1 connector3-2.sym -{ -T 20400 58900 5 10 1 1 0 0 1 -refdes=CONN1 -T 20800 58850 5 10 0 0 0 6 1 -device=CONNECTOR_3 -T 20800 59050 5 10 0 0 0 6 1 -footprint=connector(3,1) -} N 21100 58400 23100 58400 4 N 21100 58000 21700 58000 4 N 21700 58000 21700 56700 4 C 21600 56400 1 0 0 gnd-1.sym -T 21200 57500 9 10 1 0 0 0 1 -key C 23800 56400 1 0 0 gnd-1.sym N 23900 56700 23900 57800 4 C 25900 57600 1 0 0 connector2-2.sym { T 26600 58900 5 10 1 1 0 6 1 -refdes=CONN2 +refdes=J2 T 26200 58850 5 10 0 0 0 0 1 device=CONNECTOR_2 T 26200 59050 5 10 0 0 0 0 1 -footprint=connector(2,1) +footprint=connector(1,2) } N 25900 58400 24700 58400 4 N 25700 58000 25700 56700 4 @@ -43,13 +32,13 @@ T 22700 57800 5 10 0 0 270 0 1 device=POLARIZED_CAPACITOR T 22000 57400 5 10 1 1 270 0 1 -refdes=C1 +refdes=C3 T 22900 57800 5 10 0 0 270 0 1 symversion=0.1 T 22000 58000 5 10 0 0 270 0 1 footprint=rcy(200) T 22000 58100 5 10 1 1 270 0 1 -value=47uF +value=100uF } C 22100 56400 1 0 0 gnd-1.sym N 22200 57100 22200 56700 4 @@ -59,13 +48,13 @@ T 23400 57800 5 10 0 0 270 0 1 device=CAPACITOR T 23200 57800 5 10 1 1 270 0 1 -refdes=C2 +refdes=C1 T 23600 57800 5 10 0 0 270 0 1 symversion=0.1 T 22700 58200 5 10 1 1 270 0 1 value=100nF T 22700 58000 5 10 0 0 0 0 1 -footprint=0805 +footprint=acy(200) } N 22900 58000 22900 58400 4 C 22800 56400 1 0 0 gnd-1.sym @@ -75,14 +64,23 @@ T 25500 57800 5 10 0 0 270 0 1 device=CAPACITOR T 25300 57800 5 10 1 1 270 0 1 -refdes=C3 +refdes=C2 T 25700 57800 5 10 0 0 270 0 1 symversion=0.1 T 24800 58200 5 10 1 1 270 0 1 value=100nF T 24800 58000 5 10 0 0 0 0 1 -footprint=0805 +footprint=acy(200) } N 25000 58000 25000 58400 4 C 24900 56400 1 0 0 gnd-1.sym N 25000 56700 25000 57100 4 +C 21100 57600 1 0 1 connector2-2.sym +{ +T 20400 58900 5 10 1 1 0 0 1 +refdes=J1 +T 20800 58850 5 10 0 0 0 6 1 +device=CONNECTOR_2 +T 20800 59050 5 10 0 0 0 6 1 +footprint=connector(1,2) +} Index: 7805/index.html =================================================================== --- 7805/index.html (revision 24785) +++ 7805/index.html (revision 24786) @@ -5,17 +5,18 @@ A project is just a directory that holds at least the schematics, but usually also the pcb layout file and scripts.

- Start the new project by creating an empty directory. Start - gschem with an empty design and save it in the project directory. - Place the following symbols and edit/add these attributes: + Start the new project by creating an empty directory. Draw + the schematics with any schematics editor supported by pcb-rnd and + save it in this new directory. On the schematics + place the following symbols and edit/add these attributes:

Arrange and connect the pins as shown below. @@ -22,75 +23,23 @@

schematics

- Save the design as 7805.sch. -

Step 2: build script

-

- We are going to use a Makefile in this example to demonstrate - how to automate certain steps. In a fully automated project all - data exchange between the various tools (schematics editor, pcb-rnd, - simulators, etc.) is done by scripts. Generating the documentation - and exporting various other output like gerbers are usually automated - the same way. (As an alternative, all these can be done manually, from - the GUI as well.) -

- Create a new file called Makefile and edit it using your favorite text - editor to the following: -

-7805.lht: 7805.sch
-	gsch2pcb-rnd -m import 7805.sch
 
-clean:
-	rm -f 7805.cmd
-		
-

- The first rule calls the forward annotation utility, gsch2pcb-rnd to - create a forward annotation command file called 7805.cmd when the - schematics file is newer than the layout file (7805.lht). The second - rule removes such a command file to make the directory clean of - auto-generated temporary files. +

Step 2: export the netlist as needed

+

+Depending on the schematics capture software you choose, you may need to +export a netlist that can be imported in pcb-rnd. +

+TODO: create a pool node on this -

Step 3: Create the initial board

-

- The layout process usually starts when there's at least a partially - finished schematics is available. The most common workflow is that - changes and improvements in the schematics are forward annotated to - the layout. -

- Start pcb-rnd. This will load the system-installed template board - as a new, empty design. Save it in the project directory as 7805.lht. -

- Start a shell (but don't close pcb-rnd); in the project directory, - type make. This will create 7805.cmd that contains a pcb-rnd - action script that can sync a board to the information extracted from - the schematics. -

- Back in pcb-rnd, type ":ExecuteFile(7805.cmd)" and press enter. The colon - will open the CLI entry where the ExecuteFile(filename) is an action that - will load the file named and execute each line as an action. -

- At the end of the process, the layout should have all footprints. Press - 'o' and the logical connections will show up as a "rats nest". +

Step 3: lay out the board

+

+Please follow the tEDAx netlist +tutorial from step2 for laying out the board. -

Step 4: Lay out the board

-

- Move the subcircuits around. Pressing 'o' after some moves will re-optimize - the rats. As rats nest gets simpler and simpler, this can help choosing - the best placement. All components started out on the component (top) side. - Hover the mouse over the 0805 capacitors and press 'b' - this will send - them to the solder side. -

- After the placement, pick the solder layer to draw on and use the line tool - to draw the traces. Change the style to 'Power' or 'Fat' to get wider - traces. Press 'o' after drawing a few connections. When only the ground - network is left, use the rectangle tool to draw a large polygon on the - solder-gnd layer. Use the thermal tool to connect pins to the ground polygon. - The thermal tool does not work on SMD pads, they need to be connected using - lines. -

- When everything is connected, pressing 'o' will remove the last rat line. - The message log window also shows how many rats are remaining when 'o' - is pressed. The message log can be opened using the - Window/Message Log menu. +

Step 4: updates: forward annotation

+

+If you need to change the schematics later, re-export it from the schematics +editor and re-import it from pcb-rnd. If the format included importing +footprints, all new footprints will be imported. The netlist will be updated. +press {c r} after the import and update the board to reflect schematics changes. -

Step 5: updates

-

Index: 7805/sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: 7805/sch.png =================================================================== --- 7805/sch.png (nonexistent) +++ 7805/sch.png (revision 24786) Property changes on: 7805/sch.png ___________________________________________________________________ Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property