Index: src_plugins/dialogs/dlg_padstack.c
===================================================================
--- src_plugins/dialogs/dlg_padstack.c	(revision 26547)
+++ src_plugins/dialogs/dlg_padstack.c	(revision 26548)
@@ -736,6 +736,11 @@
 	pcb_gui->invalidate_all(&PCB->hidlib);
 }
 
+#define spring(dlg) \
+	PCB_DAD_BEGIN_VBOX(dlg); \
+		PCB_DAD_COMPFLAG(dlg, PCB_HATF_EXPFILL); \
+	PCB_DAD_END(dlg);
+
 void pcb_pstkedit_dialog(pse_t *pse, int target_tab)
 {
 	int n;
@@ -801,9 +806,7 @@
 					PCB_DAD_BEGIN_HBOX(dlg);
 						PCB_DAD_COMPFLAG(dlg, PCB_HATF_EXPFILL);
 						PCB_DAD_LABEL(dlg, "Settings that affect all padstacks with the same prototype");
-						PCB_DAD_BEGIN_VBOX(dlg);
-							PCB_DAD_COMPFLAG(dlg, PCB_HATF_EXPFILL);
-						PCB_DAD_END(dlg);
+						spring(dlg);
 						PCB_DAD_BEGIN_HBOX(dlg);
 							PCB_DAD_COMPFLAG(dlg, PCB_HATF_FRAME);
 							PCB_DAD_LABEL(dlg, "Prototype name:");
@@ -862,7 +865,7 @@
 					PCB_DAD_LABEL(dlg, "Hole properties:");
 						pse->hole_header = PCB_DAD_CURRENT(dlg);
 
-					PCB_DAD_BEGIN_TABLE(dlg, 4);
+					PCB_DAD_BEGIN_TABLE(dlg, 3);
 
 						PCB_DAD_LABEL(dlg, "Diameter:");
 						PCB_DAD_COORD(dlg, "");
@@ -870,11 +873,13 @@
 							PCB_DAD_MINVAL(dlg, 0);
 							PCB_DAD_MAXVAL(dlg, PCB_MM_TO_COORD(1000));
 							PCB_DAD_CHANGE_CB(dlg, pse_chg_hole);
-						PCB_DAD_LABEL(dlg, "Hole/slot plating:");
-						PCB_DAD_BOOL(dlg, "");
-							pse->hplated = PCB_DAD_CURRENT(dlg);
-							PCB_DAD_CHANGE_CB(dlg, pse_chg_hole);
-							PCB_DAD_HELP(dlg, "A plated hole galvanically connects layers");
+						PCB_DAD_BEGIN_HBOX(dlg);
+							PCB_DAD_LABEL(dlg, "Hole/slot plating:");
+							PCB_DAD_BOOL(dlg, "");
+								pse->hplated = PCB_DAD_CURRENT(dlg);
+								PCB_DAD_CHANGE_CB(dlg, pse_chg_hole);
+								PCB_DAD_HELP(dlg, "A plated hole galvanically connects layers");
+						PCB_DAD_END(dlg);
 
 						PCB_DAD_LABEL(dlg, "Hole/slot top:");
 						PCB_DAD_INTEGER(dlg, "");
@@ -883,10 +888,13 @@
 							PCB_DAD_MAXVAL(dlg, pse->pcb->LayerGroups.cache.copper_len-1);
 							PCB_DAD_CHANGE_CB(dlg, pse_chg_hole);
 							PCB_DAD_HELP(dlg, "Blind/buried via/slot: top end of the hole");
-						PCB_DAD_LABEL(dlg, "<text>");
-							pse->htop_text = PCB_DAD_CURRENT(dlg);
-						PCB_DAD_LABEL(dlg, "<layer>");
-							pse->htop_layer = PCB_DAD_CURRENT(dlg);
+						PCB_DAD_BEGIN_HBOX(dlg);
+							PCB_DAD_LABEL(dlg, "<text>");
+								pse->htop_text = PCB_DAD_CURRENT(dlg);
+							spring(dlg);
+							PCB_DAD_LABEL(dlg, "<layer>");
+								pse->htop_layer = PCB_DAD_CURRENT(dlg);
+						PCB_DAD_END(dlg);
 
 						PCB_DAD_LABEL(dlg, "Hole/slot bottom:");
 						PCB_DAD_INTEGER(dlg, "");
@@ -895,10 +903,13 @@
 							PCB_DAD_MAXVAL(dlg, pse->pcb->LayerGroups.cache.copper_len-1);
 							PCB_DAD_CHANGE_CB(dlg, pse_chg_hole);
 							PCB_DAD_HELP(dlg, "Blind/buried via/slot: bottom end of the hole");
-						PCB_DAD_LABEL(dlg, "<text>");
-							pse->hbot_text = PCB_DAD_CURRENT(dlg);
-						PCB_DAD_LABEL(dlg, "<layer>");
-							pse->hbot_layer = PCB_DAD_CURRENT(dlg);
+						PCB_DAD_BEGIN_HBOX(dlg);
+							PCB_DAD_LABEL(dlg, "<text>");
+								pse->hbot_text = PCB_DAD_CURRENT(dlg);
+							spring(dlg);
+							PCB_DAD_LABEL(dlg, "<layer>");
+								pse->hbot_layer = PCB_DAD_CURRENT(dlg);
+						PCB_DAD_END(dlg);
 					PCB_DAD_END(dlg);
 				PCB_DAD_END(dlg);
 			PCB_DAD_END(dlg);