Index: trunk/src_plugins/io_autotrax/read.c
===================================================================
--- trunk/src_plugins/io_autotrax/read.c	(revision 26986)
+++ trunk/src_plugins/io_autotrax/read.c	(revision 26987)
@@ -225,7 +225,7 @@
 		return 1;
 	return -1;
 
-TODO(": do not use strlen() for this, decide where to move this code")
+TODO("do not use strlen() for this, decide where to move this code")
 /*
 		if (strlen(t) == 0) {
 			pcb_message(PCB_MSG_ERROR, "Empty free string not placed on layout, %s:%d\n", st->Filename, st->lineno);
@@ -547,7 +547,7 @@
 	}
 
 /* now find name as string on next line and copy it */
-TODO(": can not exit above if we need to read this line")
+TODO("can not exit above if we need to read this line")
 	if (fgetline(line, sizeof(line), FP, st->lineno) == NULL) {
 		pcb_message(PCB_MSG_ERROR, "Error parsing pad text field line, %s:%d\n", st->Filename, st->lineno);
 		return -1;
@@ -648,7 +648,7 @@
 				break;
 			case 2: /* rect */
 			case 4: /* round-rect - for now */
-TODO(": generate round-rect")
+TODO("generate round-rect")
 				for(n = 0; n < 7; n++) {
 					pcb_coord_t clr = (sh[n].layer_mask & PCB_LYT_MASK) ? Clearance : 0;
 					if (sh[n].layer_mask == 0) break;
@@ -656,7 +656,7 @@
 				}
 				break;
 			case 3: /* octa */
-TODO(": generate octa")
+TODO("generate octa")
 			default:
 				pcb_message(PCB_MSG_ERROR, "Unsupported FP shape: %d, %s:%d.\n", Shape, st->Filename, st->lineno);
 				return 0;
@@ -699,7 +699,7 @@
 			valid &= success;
 			Y2 = pcb_get_value_ex(argv[3], NULL, NULL, NULL, "mil", &success);
 			valid &= success;
-TODO(": do not use get_value_ex for plain integers (revise the whole file for this)")
+TODO("do not use get_value_ex for plain integers (revise the whole file for this)")
 			autotrax_layer = pcb_get_value_ex(argv[4], NULL, NULL, NULL, NULL, &success);
 			valid &= (success && (autotrax_layer > 0) && (autotrax_layer < 14));
 			qparse_free(argc, &argv);
@@ -716,7 +716,7 @@
 		return -1;
 	}
 
-TODO(": figure if autotrax really converts layer 1 and 6 polygons to pads")
+TODO("figure if autotrax really converts layer 1 and 6 polygons to pads")
 	if ((subc == NULL) || ((autotrax_layer != 1) && (autotrax_layer != 6))) {
 		ly = autotrax_get_layer(st, subc, autotrax_layer, "polygon");
 		if (ly == NULL)
@@ -1000,7 +1000,7 @@
 			valid &= success;
 			module_Y = pcb_get_value_ex(argv[1], NULL, NULL, NULL, "mil", &success);
 			valid &= success;
-TODO(": load placement status and apply PCB_FLAG_LOCK if needed")
+TODO("load placement status and apply PCB_FLAG_LOCK if needed")
 			qparse_free(argc, &argv);
 		}
 		else {
@@ -1042,7 +1042,7 @@
 			}
 		}
 		else if (length >= 2) {
-TODO(": this does not handle return -1")
+TODO("this does not handle return -1")
 			if (strncmp(s, "CT", 2) == 0) {
 				nonempty |= rdax_track(st, FP, new_module);
 			}
Index: trunk/src_plugins/io_autotrax/write.c
===================================================================
--- trunk/src_plugins/io_autotrax/write.c	(revision 26986)
+++ trunk/src_plugins/io_autotrax/write.c	(revision 26987)
@@ -189,7 +189,7 @@
 		h = y2 - y1;
 		drill_dia = 0;
 
-TODO(": need to figure which side the padstack is on!")
+TODO("need to figure which side the padstack is on!")
 		alayer = 1;
 	}
 	else {
@@ -217,8 +217,8 @@
 	else
 		fputs("FP ", ctx->f);
 
-TODO(": figure which is the gnd and which is the power plane")
-TODO(": add checks for thermals: only gnd/pwr can have them, warn for others")
+TODO("figure which is the gnd and which is the power plane")
+TODO("add checks for thermals: only gnd/pwr can have them, warn for others")
 
 	pcb_fprintf(ctx->f, "%.0ml %.0ml %.0ml %.0ml %d %.0ml 1 %d\r\n",
 		x+dx, PCB->hidlib.size_y - (y+dy), w, h,
@@ -437,7 +437,7 @@
 
 	int index = 0;
 
-TODO(": why do we hardwire this here?")
+TODO("why do we hardwire this here?")
 	default_stroke_thickness = 200000;
 
 	/* write information about non empty layers */
@@ -447,7 +447,7 @@
 			int direction;
 			
 			if (pcb_text_old_direction(&direction, text->rot) != 0) {
-TODO(": indicate save incompatibility")
+TODO("indicate save incompatibility")
 			}
 
 			if (current_layer < 9) { /* copper or silk layer text */
@@ -500,11 +500,11 @@
 	pcb_box_t *box = &subc->BoundingBox;
 	pcb_coord_t xPos, yPos, yPos2, yPos3;
 
-TODO(": do not hardcode things like this, especially when actual data is available")
+TODO("do not hardcode things like this, especially when actual data is available")
 	pcb_coord_t text_offset = PCB_MIL_TO_COORD(400); /* this gives good placement of refdes relative to element */
 
-TODO(": rename these variables to something more expressive")
-TODO(": instead of hardwiring coords, just read existing dyntex coords")
+TODO("rename these variables to something more expressive")
+TODO("instead of hardwiring coords, just read existing dyntex coords")
 	xPos = (box->X1 + box->X2) / 2;
 	yPos = PCB->hidlib.size_y - (box->Y1 - text_offset);
 	yPos2 = yPos - PCB_MIL_TO_COORD(200);
@@ -512,7 +512,7 @@
 
 	pcb_subc_get_side(subc, &on_bottom);
 
-TODO(": do not hardwire these layers, even if the autotrax format hardwires them - look them up from the static table, let the hardwiring happen only at one place")
+TODO("do not hardwire these layers, even if the autotrax format hardwires them - look them up from the static table, let the hardwiring happen only at one place")
 	if (on_bottom)
 		silk_layer = 8;
 	else
@@ -564,7 +564,7 @@
 			if (pcb_cpoly_is_simple_rect(polygon)) {
 				pcb_trace(" simple rectangular polyogon\n");
 
-TODO(": why do we recalculate the bounding box here?")
+TODO("why do we recalculate the bounding box here?")
 				minx = maxx = polygon->Points[0].X;
 				miny = maxy = polygon->Points[0].Y;
 
@@ -593,7 +593,7 @@
 				pcb_coord_t Thickness;
 				Thickness = PCB_MIL_TO_COORD(10);
 				autotrax_cpoly_hatch_lines(ctx, polygon, PCB_CPOLY_HATCH_HORIZONTAL | PCB_CPOLY_HATCH_VERTICAL, Thickness * 3, Thickness, current_layer, dx, dy);
-TODO(": do we really need to reimplement this, can not cpoly_hatch_lines handle it?")
+TODO("do we really need to reimplement this, can not cpoly_hatch_lines handle it?")
 				for(pa = pcb_poly_island_first(polygon, &poly_it); pa != NULL; pa = pcb_poly_island_next(&poly_it)) {
 					/* now generate cross hatch lines for polygon island export */
 					pcb_pline_t *pl, *track;
@@ -668,7 +668,7 @@
 	wctx.f = FP;
 	wctx.pcb = PCB;
 
-TODO(": this is a bug - exporting to a file shall not change the content we are exporting")
+TODO("this is a bug - exporting to a file shall not change the content we are exporting")
 	if (pcb_board_normalize(PCB) < 0) {
 		pcb_message(PCB_MSG_ERROR, "Unable to normalise layout prior to attempting export.\n");
 		return -1;