+ The boxsym syntax is a plain text, line based, hierarchical file format + with a syntax simylar to tEDAx. Leading whitespace in lines are ignored. + Empty lines and lines starting with a hashmark (#) are ignored. The first + word of a line is a command. +
+ If the command is
+ Commands issued outside of any begin-end blocks are said to be made in + global scope. +
+ There can be only one refdes line, in gloval scope. The argument is + a single word, the refdes attribute. If no refdes is specified, the + default refdes is used. +
+ Attributes are symbol attributes. Attributes specified in the global scope + will be present in every symbol generated from the file. Attributes specified + for a slot will be present in the slot's symbol and in the monolith symbol. +
+ An attribute is defined in the following form: +
+
+ Key is a single word, value is anything up to the end of the line. This
+ defintion creates the attribute and places a dyntext+floater text object
+ printing the value of the attribute. If command is
+ Pins are defined using a pin subtree: begin pin pinname, then lines defining + pin properties and then an end pin. Pinname should be the textual, human + readable name of the pin (also used as an input for the optional devmap), + not the physica pin number. +
For example: +
+begin pin Vcc + num 14 + loc top +end pin +begin pin B + num 2:5:10:13 + loc left + dir in + invcirc +end pin ++
+ Within the pin block the
+ The mandatory
+ If a
+ If
+ By default pins are listed per side (loc), tightly packed, in order of + appearance in the file from the start of the side. This can be changed + using pinalign lines in global or slot scope: +
+pinalign left center ++
+ will arrange left side pins on the center (vertically). +
+ The typical example is an MCU which is split up into a couple of + boxes: a few boxes per port groups and another few per peripheral + types. Each box represents a slot that appears only once in the MCU. +
+ Another typical example is logic ICs, e.g. 7400 implemented in two + different slot symbols: one for power (Vcc and gnd), presents once + in the component, and one for a 3 pin gate, same box used 4 times + for 4 different slots. +
+ An inhomogenous slot symbol does not have any pin in global scope, but + defines one or more "begin slot slotname" subtrees for all the different + type of slots. If the same slot appears multiple times in the component, + it needs to be defined only once (and multiple pin numbers assigned + in pin definitions.) +
+refdes U?? +attr_invis sym-source sch-rnd default symbol lib +attr_invis sym-copyright (C) 2022 Tibor 'Igor2' Palinkas +attr_invis sym-license-dist GPLv2+ +attr_invis sym-license-use Public Domain + +pinalign bottom center +pinalign left center +pinalign right center + +shape box +begin pin in + num 1 + loc left +end pin + +begin pin gnd + num 2 + loc bottom +end pin + +begin pin out + num 3 + loc right +end pin + + ++
+refdes U?? + +pinalign right center +pinalign bottom center +pinalign top center +attr device 7400 + +begin slot power + shape box + begin pin Vcc + num 14 + loc top + end pin + begin pin gnd + num 7 + loc bottom + end pin + pinalign top center + pinalign bottom center +end slot + + +begin slot logic + attr device 7400 + attr_both slot 1 + + begin pin A + num 1:4:9:12 + loc left + dir in + end pin + + begin pin B + num 2:5:10:13 + loc left + dir in + end pin + + begin pin Z + num 3:6:8:11 + loc right + dir out + invcirc + end pin + + pinalign left center + pinalign right center +end slot + + ++