Index: read.c =================================================================== --- read.c (revision 29694) +++ read.c (revision 29695) @@ -344,7 +344,7 @@ break; case 20: /*199: 20 is dimension, 199 is contour */ grp = pcb_get_grp_new_intern(st->pcb, -1); - ly->lid = pcb_layer_create(st->pcb, grp - st->pcb->LayerGroups.grp, ly->name); + ly->lid = pcb_layer_create(st->pcb, grp - st->pcb->LayerGroups.grp, ly->name, 0); pcb_layergrp_fix_turn_to_outline(grp); break; @@ -352,7 +352,7 @@ if ((id > 1) && (id < 16)) { /* new internal layer */ grp = pcb_get_grp_new_intern(st->pcb, -1); - ly->lid = pcb_layer_create(st->pcb, grp - st->pcb->LayerGroups.grp, ly->name); + ly->lid = pcb_layer_create(st->pcb, grp - st->pcb->LayerGroups.grp, ly->name, 0); } } if (typ != 0) { @@ -359,7 +359,7 @@ if (reuse) pcb_layer_list(st->pcb, typ, &ly->lid, 1); if ((ly->lid < 0) && (pcb_layergrp_list(st->pcb, typ, &gid, 1) > 0)) - ly->lid = pcb_layer_create(st->pcb, gid, ly->name); + ly->lid = pcb_layer_create(st->pcb, gid, ly->name, 0); } } } @@ -406,7 +406,7 @@ ly->visible = 0; ly->active = 1; pcb_layergrp_list(st->pcb, typ, &gid, 1); - ly->lid = pcb_layer_create(st->pcb, gid, ly->name); + ly->lid = pcb_layer_create(st->pcb, gid, ly->name, 0); } else return NULL; /* not found and not supported */ Index: read_dru.c =================================================================== --- read_dru.c (revision 29694) +++ read_dru.c (revision 29695) @@ -216,14 +216,14 @@ /* set up layers */ pcb_layer_group_setup_default(pcb); if (pcb_layergrp_list(pcb, PCB_LYT_COPPER | PCB_LYT_TOP, &gid, 1)) - pcb_layer_create(pcb, gid, "top_copper"); + pcb_layer_create(pcb, gid, "top_copper", 0); if (pcb_layergrp_list(pcb, PCB_LYT_COPPER | PCB_LYT_BOTTOM, &gid, 1)) - pcb_layer_create(pcb, gid, "bottom_copper"); + pcb_layer_create(pcb, gid, "bottom_copper", 0); num_layers--; for(n = 0; n < num_layers; n++) { pcb_layergrp_t *grp = pcb_get_grp_new_intern(pcb, -1); sprintf(tmp, "signal_%d", n); - pcb_layer_create(pcb, grp - pcb->LayerGroups.grp, tmp); + pcb_layer_create(pcb, grp - pcb->LayerGroups.grp, tmp, 0); } pcb_layer_group_setup_silks(pcb);