Index: dlg.c
===================================================================
--- dlg.c	(revision 30277)
+++ dlg.c	(revision 30278)
@@ -72,10 +72,15 @@
 	if (nd != NULL) {
 		pcb_hid_attribute_t *atxt = &ctx->dlg[ctx->wquery];
 		pcb_hid_text_t *txt = atxt->wdata;
+		int *dis, dis_ = 0;
 
+		dis = drc_get_disable(ctx->rule);
+		if (dis == NULL)
+			dis = &dis_;
+
 		PCB_DAD_SET_VALUE(ctx->dlg_hid_ctx, ctx->wtype,    str, textval(nd, "type"));
 		PCB_DAD_SET_VALUE(ctx->dlg_hid_ctx, ctx->wtitle,   str, textval(nd, "title"));
-		PCB_DAD_SET_VALUE(ctx->dlg_hid_ctx, ctx->wdisable, str, boolval(nd, "disable"));
+		PCB_DAD_SET_VALUE(ctx->dlg_hid_ctx, ctx->wdisable, str, *dis);
 		PCB_DAD_SET_VALUE(ctx->dlg_hid_ctx, ctx->wdesc,    str, textval(nd, "desc"));
 
 		txt->hid_set_text(atxt, ctx->dlg_hid_ctx, PCB_HID_TEXT_REPLACE, textval(nd, "query"));
@@ -242,14 +247,19 @@
 	cell[3] = NULL;
 
 	pcb_conflist_foreach(&conf_drc_query.plugins.drc_query.rules, &it, i) {
+		int *dis, dis_ = 0;
 		conf_role_t role;
 		lht_node_t *rule = i->prop.src;
 		if (rule->type != LHT_HASH)
 			continue;
 
+		dis = drc_get_disable(rule->name);
+		if (dis == NULL)
+			dis = &dis_;
+
 		role = pcb_conf_lookup_role(rule);
 		cell[0] = pcb_conf_role_name(role);
-		cell[1] = load_int(rule, i, "disable", 0) ? "YES" : "no";
+		cell[1] = *dis ? "YES" : "no";
 		cell[2] = rule->name;
 		pcb_dad_tree_append(attr, NULL, cell);
 	}
Index: drc_query.c
===================================================================
--- drc_query.c	(revision 30277)
+++ drc_query.c	(revision 30278)
@@ -63,7 +63,6 @@
 	const char *type;
 	const char *title;
 	const char *desc;
-	unsigned disable:1;
 } drc_qry_ctx_t;
 
 pcb_coord_t load_obj_const(pcb_obj_qry_const_t *cnst)
@@ -201,11 +200,21 @@
 	return l;
 }
 
+static int *drc_get_disable(const char *name)
+{
+	char *path = pcb_concat("design/drc_disable/", name, NULL);
+	conf_native_t *nat = pcb_conf_get_field(path);
+	free(path);
+	if ((nat == NULL) || (nat->type != CFN_BOOLEAN))
+		return NULL;
+	return nat->val.boolean;
+}
+
 static void pcb_drc_query(pcb_hidlib_t *hidlib, void *user_data, int argc, pcb_event_arg_t argv[])
 {
 	gdl_iterator_t it;
 	pcb_conf_listitem_t *i;
-	long cnt = 0, disable;
+	long cnt = 0;
 
 	if (conf_drc_query.plugins.drc_query.disable)
 		return;
@@ -212,13 +221,14 @@
 
 	pcb_conflist_foreach(&conf_drc_query.plugins.drc_query.rules, &it, i) {
 		lht_node_t *rule = i->prop.src;
+		int *dis;
 		if (rule->type != LHT_HASH) {
 			pcb_message(PCB_MSG_ERROR, "drc_query: rule %s is not a hash\n", i->name);
 			continue;
 		}
 
-		disable = load_int(rule, i, "disable", 0);
-		if (disable)
+		dis = drc_get_disable(i->name);
+		if ((dis != NULL) && (*dis == 0))
 			continue;
 
 		cnt += drc_qry_exec((pcb_board_t *)hidlib, &pcb_drc_lst, i,
Index: drc_query.conf
===================================================================
--- drc_query.conf	(revision 30277)
+++ drc_query.conf	(revision 30278)
@@ -30,7 +30,6 @@
 						type = pair hole
 						title = overlapping holes
 						desc = padstack holes overlap
-						disable = 0
 						query = {
 rule overlap
 let A @.type==PSTK
@@ -43,7 +42,6 @@
 						type = broken net
 						title = insufficient overlap
 						desc = the overlap between two objects in the net is insufficient and can lead to broken network during board fabrication
-						disable = 0
 						query = {
 rule net brk
 let N netlist()
@@ -56,7 +54,6 @@
 						type = shorted nets
 						title = net too close to other net
 						desc = insufficient clearance between an object of the network and objects of other networks
-						disable = 0
 						query = {
 rule net short
 let N netlist()