Index: read.c =================================================================== --- read.c (revision 30902) +++ read.c (revision 30903) @@ -106,13 +106,13 @@ pcb_layer_t *primitive_ly; /* for gr_ objects: if not NULL, use this layer and expect no layer specified in the file */ pcb_subc_t *primitive_subc; /* for gr_ objects: if not NULL, object is being added under this subc (apply offs) */ - pcb_coord_t width[DIM_max]; - pcb_coord_t height[DIM_max]; - pcb_coord_t dim_valid[DIM_max]; + rnd_coord_t width[DIM_max]; + rnd_coord_t height[DIM_max]; + rnd_coord_t dim_valid[DIM_max]; /* setup */ - pcb_coord_t pad_to_mask_clearance; - pcb_coord_t zone_clearance; + rnd_coord_t pad_to_mask_clearance; + rnd_coord_t zone_clearance; /* delayed actions */ zone_connect_t *zc_head; @@ -148,7 +148,7 @@ gds_append(&str, '\n'); - pcb_message(PCB_MSG_ERROR, "%s", str.array); + rnd_message(PCB_MSG_ERROR, "%s", str.array); gds_uninit(&str); return -1; @@ -168,7 +168,7 @@ gds_append(&str, '\n'); - pcb_message(PCB_MSG_WARNING, "%s", str.array); + rnd_message(PCB_MSG_WARNING, "%s", str.array); gds_uninit(&str); return 0; @@ -503,7 +503,7 @@ pcb_idx = kicad_get_layeridx(st, layer_name); lnm = layer_name; if (pcb_idx < 0) { - pcb_message(PCB_MSG_ERROR, "\tfp_* layer '%s' not found for module object, using unbound subc layer instead.\n", layer_name); + rnd_message(PCB_MSG_ERROR, "\tfp_* layer '%s' not found for module object, using unbound subc layer instead.\n", layer_name); lyt = PCB_LYT_VIRTUAL; comb = 0; return pcb_subc_get_layer(subc, lyt, comb, 1, lnm, pcb_true); @@ -515,7 +515,7 @@ if (lid >= 0) return &subc->data->Layer[lid]; - pcb_message(PCB_MSG_ERROR, "\tfp_* layer '%s' not found for module object, using module layer '%s' instead.\n", layer_name, default_layer_name); + rnd_message(PCB_MSG_ERROR, "\tfp_* layer '%s' not found for module object, using module layer '%s' instead.\n", layer_name, default_layer_name); pcb_idx = kicad_get_layeridx(st, default_layer_name); if (pcb_idx < 0) return NULL; @@ -670,7 +670,7 @@ return kicad_error(missnode, "Missing child node for " errmsg); \ } while(0) \ -/* same as PARSE_DOUBLE() but res is a pcb_coord_t, input string is in mm */ +/* same as PARSE_DOUBLE() but res is a rnd_coord_t, input string is in mm */ #define PARSE_COORD(res, missnode, node, errmsg) \ do { \ double __dtmp__; \ @@ -718,7 +718,7 @@ break; case KICAD_COORD: { - pcb_coord_t *d = (pcb_coord_t *)dst; + rnd_coord_t *d = (rnd_coord_t *)dst; PARSE_COORD(*d, NULL, subtree->children, ""); } break; @@ -810,7 +810,7 @@ int i; unsigned long tally = 0, required; double rotdeg = 0.0; /* default is horizontal */ - pcb_coord_t X, Y, thickness = 0; + rnd_coord_t X, Y, thickness = 0; int scaling = 100; int mirrored = 0; int align = 0; /* -1 for left, 0 for center and +1 for right */ @@ -832,7 +832,7 @@ PARSE_DOUBLE(rotdeg, NULL, n->children->next->next, "text rotation"); rotdeg -= mod_rot; if (subc != NULL) { - pcb_coord_t sx, sy; + rnd_coord_t sx, sy; if (pcb_subc_get_origin(subc, &sx, &sy) == 0) { X += sx; Y += sy; @@ -911,7 +911,7 @@ return kicad_error(subtree, "failed to create text due to missing fields"); { - pcb_coord_t mx, my, xalign, tw, th; + rnd_coord_t mx, my, xalign, tw, th; int swap; pcb_text_t txt; @@ -993,7 +993,7 @@ static int kicad_parse_target(read_state_t *st, gsxl_node_t *subtree) { unsigned long tally = 0, required; - pcb_coord_t x, y, thick = PCB_MM_TO_COORD(0.15); + rnd_coord_t x, y, thick = PCB_MM_TO_COORD(0.15); double size = 5.0; pcb_layer_t *ly = NULL; pcb_subc_t *subc; @@ -1076,7 +1076,7 @@ { gsxl_node_t *n; unsigned long tally = 0, required; - pcb_coord_t x1, y1, x2, y2, thickness, clearance; + rnd_coord_t x1, y1, x2, y2, thickness, clearance; pcb_flag_t flg = pcb_flag_make(flag); pcb_layer_t *ly = NULL; pcb_line_t *line; @@ -1159,7 +1159,7 @@ subc = st->primitive_subc; if (subc != NULL) { - pcb_coord_t sx, sy; + rnd_coord_t sx, sy; if (pcb_subc_get_origin(subc, &sx, &sy) == 0) { x1 += sx; y1 += sy; @@ -1184,7 +1184,7 @@ { gsxl_node_t *n; unsigned long tally = 0, required; - pcb_coord_t cx, cy, endx, endy, thickness, clearance, deltax, deltay; + rnd_coord_t cx, cy, endx, endy, thickness, clearance, deltax, deltay; pcb_angle_t end_angle = 0.0, delta = 360.0; /* these defaults allow a gr_circle to be parsed, which does not specify (angle XXX) */ pcb_flag_t flg = pcb_flag_make(0); /* start with something bland here */ pcb_layer_t *ly = NULL; @@ -1249,7 +1249,7 @@ { pcb_angle_t start_angle; - pcb_coord_t width, height; + rnd_coord_t width, height; width = height = pcb_distance(cx, cy, endx, endy); /* calculate radius of arc */ deltax = endx - cx; @@ -1274,7 +1274,7 @@ subc = st->primitive_subc; if (subc != NULL) { - pcb_coord_t sx, sy; + rnd_coord_t sx, sy; if (pcb_subc_get_origin(subc, &sx, &sy) == 0) { cx += sx; cy += sy; @@ -1300,7 +1300,7 @@ gsxl_node_t *n, *nly1, *nly2; unsigned long tally = 0, required; int blind_cnt = 0; - pcb_coord_t x, y, thickness, clearance, mask, drill; /* not sure what to do with mask */ + rnd_coord_t x, y, thickness, clearance, mask, drill; /* not sure what to do with mask */ pcb_layer_t *ly1, *ly2; /* blind/buried: from-to layers */ pcb_pstk_t *ps; @@ -1619,7 +1619,7 @@ -static void kicad_slot_shape(pcb_pstk_shape_t *shape, pcb_coord_t sx, pcb_coord_t sy) +static void kicad_slot_shape(pcb_pstk_shape_t *shape, rnd_coord_t sx, rnd_coord_t sy) { shape->shape = PCB_PSSH_LINE; if (sx > sy) { /* horizontal */ @@ -1645,10 +1645,10 @@ /* check if shape is wanted on a given layer - SMD version */ #define LYSHS(loc, typ) ((layers->want[loc] & (PCB_LYT_ ## typ))) -static pcb_pstk_t *kicad_make_pad_thr(read_state_t *st, gsxl_node_t *subtree, pcb_subc_t *subc, pcb_coord_t X, pcb_coord_t Y, pcb_coord_t padXsize, pcb_coord_t padYsize, pcb_coord_t clearance, pcb_coord_t mask, pcb_coord_t paste, double paste_ratio, pcb_coord_t drillx, pcb_coord_t drilly, const char *pad_shape, int plated, kicad_padly_t *layers, double shape_arg, double shape_arg2) +static pcb_pstk_t *kicad_make_pad_thr(read_state_t *st, gsxl_node_t *subtree, pcb_subc_t *subc, rnd_coord_t X, rnd_coord_t Y, rnd_coord_t padXsize, rnd_coord_t padYsize, rnd_coord_t clearance, rnd_coord_t mask, rnd_coord_t paste, double paste_ratio, rnd_coord_t drillx, rnd_coord_t drilly, const char *pad_shape, int plated, kicad_padly_t *layers, double shape_arg, double shape_arg2) { int len = 0, slot = (drillx != drilly); - pcb_coord_t drill = 0; + rnd_coord_t drill = 0; if (pad_shape == NULL) { kicad_error(subtree, "pin with no shape"); @@ -1665,7 +1665,7 @@ padstack and add the custom shapes as heavy terminal together with the padstack */ pcb_pstk_shape_t sh[9]; - pcb_coord_t dy = PCB_MM_TO_COORD(shape_arg), dx = PCB_MM_TO_COORD(shape_arg2); /* x;y and 1;2 swapped intentionally - kicad does it like that */ + rnd_coord_t dy = PCB_MM_TO_COORD(shape_arg), dx = PCB_MM_TO_COORD(shape_arg2); /* x;y and 1;2 swapped intentionally - kicad does it like that */ memset(sh, 0, sizeof(sh)); if (LYSHT(TOP, MASK)) {sh[len].layer_mask = PCB_LYT_TOP | PCB_LYT_MASK; sh[len].comb = PCB_LYC_SUB | PCB_LYC_AUTO; pcb_shape_rect_trdelta(&sh[len++], padXsize+mask*2, padYsize+mask*2, dx, dy);} if (LYSHT(BOTTOM, MASK)) {sh[len].layer_mask = PCB_LYT_BOTTOM | PCB_LYT_MASK; sh[len].comb = PCB_LYC_SUB | PCB_LYC_AUTO; pcb_shape_rect_trdelta(&sh[len++], padXsize+mask*2, padYsize+mask*2, dx, dy);} @@ -1724,7 +1724,7 @@ return NULL; } -static pcb_pstk_t *kicad_make_pad_smd(read_state_t *st, gsxl_node_t *subtree, pcb_subc_t *subc, pcb_coord_t X, pcb_coord_t Y, pcb_coord_t padXsize, pcb_coord_t padYsize, pcb_coord_t clearance, pcb_coord_t mask, pcb_coord_t paste, double paste_ratio, const char *pad_shape, pcb_layer_type_t side, kicad_padly_t *layers, double shape_arg, double shape_arg2) +static pcb_pstk_t *kicad_make_pad_smd(read_state_t *st, gsxl_node_t *subtree, pcb_subc_t *subc, rnd_coord_t X, rnd_coord_t Y, rnd_coord_t padXsize, rnd_coord_t padYsize, rnd_coord_t clearance, rnd_coord_t mask, rnd_coord_t paste, double paste_ratio, const char *pad_shape, pcb_layer_type_t side, kicad_padly_t *layers, double shape_arg, double shape_arg2) { int len = 0; @@ -1743,7 +1743,7 @@ if ((strcmp(pad_shape, "rect") == 0) || (strcmp(pad_shape, "trapezoid") == 0) || (strcmp(pad_shape, "custom") == 0)) { /* "custom" pads: see comment in kicad_make_pad_thr() */ pcb_pstk_shape_t sh[4]; - pcb_coord_t dy = PCB_MM_TO_COORD(shape_arg), dx = PCB_MM_TO_COORD(shape_arg2); /* x;y and 1;2 swapped intentionally - kicad does it like that */ + rnd_coord_t dy = PCB_MM_TO_COORD(shape_arg), dx = PCB_MM_TO_COORD(shape_arg2); /* x;y and 1;2 swapped intentionally - kicad does it like that */ memset(sh, 0, sizeof(sh)); if (LYSHS(side, MASK)) {sh[len].layer_mask = side | PCB_LYT_MASK; sh[len].comb = PCB_LYC_SUB | PCB_LYC_AUTO; pcb_shape_rect_trdelta(&sh[len++], padXsize+mask*2, padYsize+mask*2, dx, dy);} if (LYSHS(side, PASTE)) {sh[len].layer_mask = side | PCB_LYT_PASTE; sh[len].comb = PCB_LYC_AUTO; pcb_shape_rect_trdelta(&sh[len++], padXsize * paste_ratio + paste*2, padYsize * paste_ratio + paste*2, dx, dy);} @@ -1790,7 +1790,7 @@ #undef LYSHT #undef LYSHS -static int kicad_make_pad(read_state_t *st, gsxl_node_t *subtree, pcb_subc_t *subc, const char *netname, int throughHole, int plated, pcb_coord_t moduleX, pcb_coord_t moduleY, pcb_coord_t X, pcb_coord_t Y, pcb_coord_t padXsize, pcb_coord_t padYsize, double pad_rot, unsigned int moduleRotation, pcb_coord_t clearance, pcb_coord_t mask, pcb_coord_t paste, double paste_ratio, int zone_connect, pcb_coord_t drillx, pcb_coord_t drilly, const char *pin_name, const char *pad_shape, unsigned long *featureTally, int *moduleEmpty, pcb_layer_type_t smd_side, kicad_padly_t *layers, double shape_arg, double shape_arg2) +static int kicad_make_pad(read_state_t *st, gsxl_node_t *subtree, pcb_subc_t *subc, const char *netname, int throughHole, int plated, rnd_coord_t moduleX, rnd_coord_t moduleY, rnd_coord_t X, rnd_coord_t Y, rnd_coord_t padXsize, rnd_coord_t padYsize, double pad_rot, unsigned int moduleRotation, rnd_coord_t clearance, rnd_coord_t mask, rnd_coord_t paste, double paste_ratio, int zone_connect, rnd_coord_t drillx, rnd_coord_t drilly, const char *pin_name, const char *pad_shape, unsigned long *featureTally, int *moduleEmpty, pcb_layer_type_t smd_side, kicad_padly_t *layers, double shape_arg, double shape_arg2) { pcb_pstk_t *ps; unsigned long required; @@ -2018,11 +2018,11 @@ } TODO("eliminate this forward declaration by reordering the code") -static int kicad_parse_any_poly(read_state_t *st, gsxl_node_t *subtree, pcb_subc_t *subc, pcb_coord_t modx, pcb_coord_t mody); +static int kicad_parse_any_poly(read_state_t *st, gsxl_node_t *subtree, pcb_subc_t *subc, rnd_coord_t modx, rnd_coord_t mody); static int kicad_parse_gr_poly(read_state_t *st, gsxl_node_t *subtree) { - pcb_coord_t sx = 0, sy = 0; + rnd_coord_t sx = 0, sy = 0; pcb_subc_get_origin(st->primitive_subc, &sx, &sy); return kicad_parse_any_poly(st, subtree, st->primitive_subc, sx, sy); } @@ -2082,10 +2082,10 @@ } -static int kicad_parse_pad(read_state_t *st, gsxl_node_t *n, pcb_subc_t *subc, unsigned long *tally, pcb_coord_t moduleX, pcb_coord_t moduleY, unsigned int moduleRotation, pcb_coord_t mod_clr, pcb_coord_t mod_mask, pcb_coord_t mod_paste, double mod_paste_ratio, int mod_zone_connect, int *moduleEmpty) +static int kicad_parse_pad(read_state_t *st, gsxl_node_t *n, pcb_subc_t *subc, unsigned long *tally, rnd_coord_t moduleX, rnd_coord_t moduleY, unsigned int moduleRotation, rnd_coord_t mod_clr, rnd_coord_t mod_mask, rnd_coord_t mod_paste, double mod_paste_ratio, int mod_zone_connect, int *moduleEmpty) { gsxl_node_t *m; - pcb_coord_t x, y, drillx, drilly, sx, sy, clearance, mask = st->pad_to_mask_clearance*2, paste = 0; + rnd_coord_t x, y, drillx, drilly, sx, sy, clearance, mask = st->pad_to_mask_clearance*2, paste = 0; const char *netname = NULL; char *pin_name = NULL, *pad_shape = NULL; unsigned long feature_tally = 0; @@ -2247,10 +2247,10 @@ return 0; } -static int kicad_parse_poly_pts(read_state_t *st, gsxl_node_t *subtree, pcb_poly_t *polygon, pcb_coord_t xo, pcb_coord_t yo) +static int kicad_parse_poly_pts(read_state_t *st, gsxl_node_t *subtree, pcb_poly_t *polygon, rnd_coord_t xo, rnd_coord_t yo) { gsxl_node_t *m; - pcb_coord_t x, y; + rnd_coord_t x, y; if ((subtree == NULL) || (subtree->str == NULL)) return kicad_error(subtree, "error parsing empty polygon."); @@ -2269,11 +2269,11 @@ return 0; } -static int kicad_parse_any_poly(read_state_t *st, gsxl_node_t *subtree, pcb_subc_t *subc, pcb_coord_t modx, pcb_coord_t mody) +static int kicad_parse_any_poly(read_state_t *st, gsxl_node_t *subtree, pcb_subc_t *subc, rnd_coord_t modx, rnd_coord_t mody) { gsxl_node_t *n, *npts = NULL; pcb_layer_t *ly = NULL; - pcb_coord_t width = 0; + rnd_coord_t width = 0; unsigned long tally = 0; pcb_poly_t *poly; pcb_flag_t flags = pcb_flag_make(PCB_FLAG_CLEARPOLY); @@ -2330,7 +2330,7 @@ return 0; } -static int kicad_parse_fp_poly(read_state_t *st, gsxl_node_t *subtree, pcb_subc_t *subc, pcb_coord_t modx, pcb_coord_t mody) +static int kicad_parse_fp_poly(read_state_t *st, gsxl_node_t *subtree, pcb_subc_t *subc, rnd_coord_t modx, rnd_coord_t mody) { return kicad_parse_any_poly(st, subtree, subc, modx, mody); } @@ -2344,7 +2344,7 @@ int mod_zone_connect = 1; /* default seems to be connect; see CUCP#57, case labeled "-1" */ double mod_rot = 0, mod_paste_ratio = 0; unsigned long tally = 0; - pcb_coord_t mod_x = 0, mod_y = 0, mod_clr = UNSPECIFIED, mod_mask = UNSPECIFIED, mod_paste = UNSPECIFIED; + rnd_coord_t mod_x = 0, mod_y = 0, mod_clr = UNSPECIFIED, mod_mask = UNSPECIFIED, mod_paste = UNSPECIFIED; char *mod_name; pcb_subc_t *subc = NULL; @@ -2777,7 +2777,7 @@ pcb_layer_auto_fixup(Ptr); if (pcb_board_normalize(Ptr) > 0) - pcb_message(PCB_MSG_WARNING, "Had to make changes to the coords so that the design fits the board.\n"); + rnd_message(PCB_MSG_WARNING, "Had to make changes to the coords so that the design fits the board.\n"); pcb_layer_colors_from_conf(Ptr, 1); { /* free layer hack */ @@ -2822,13 +2822,13 @@ if (res != GSX_RES_EOE) { if (!pcb_io_err_inhibit) - pcb_message(PCB_MSG_ERROR, "Error parsing s-expression '%s'\n", name); + rnd_message(PCB_MSG_ERROR, "Error parsing s-expression '%s'\n", name); gsxl_uninit(&st.dom); return -1; } if ((st.dom.root->str == NULL) || (strcmp(st.dom.root->str, "module") != 0)) { - pcb_message(PCB_MSG_ERROR, "Wrong root node '%s', expected 'module'\n", st.dom.root->str); + rnd_message(PCB_MSG_ERROR, "Wrong root node '%s', expected 'module'\n", st.dom.root->str); gsxl_uninit(&st.dom); return -1; } Index: read_net.c =================================================================== --- read_net.c (revision 30902) +++ read_net.c (revision 30903) @@ -49,7 +49,7 @@ #define if_strval(node, name) \ if (strcmp(node->str, #name) == 0) { \ if (name != NULL) { \ - pcb_message(PCB_MSG_ERROR, "Invalid eeschema: multiple %s subtrees\n", #name); \ + rnd_message(PCB_MSG_ERROR, "Invalid eeschema: multiple %s subtrees\n", #name); \ return -1; \ } \ if (node->children != NULL) \ @@ -59,7 +59,7 @@ #define if_subtree(node, name) \ if (strcmp(node->str, #name) == 0) { \ if (name != NULL) { \ - pcb_message(PCB_MSG_ERROR, "Invalid eeschema: multiple %s subtrees\n", #name); \ + rnd_message(PCB_MSG_ERROR, "Invalid eeschema: multiple %s subtrees\n", #name); \ return -1; \ } \ name = node; \ @@ -67,7 +67,7 @@ #define req_subtree(name) \ if (name == NULL) { \ - pcb_message(PCB_MSG_ERROR, "Invalid eeschema: missing %s subtree\n", #name); \ + rnd_message(PCB_MSG_ERROR, "Invalid eeschema: missing %s subtree\n", #name); \ return -1; \ } \ @@ -78,7 +78,7 @@ /* check the header */ if (strcmp(dom->root->str, "export") != 0) { - pcb_message(PCB_MSG_ERROR, "Invalid eeschema netlist header: not an export\n"); + rnd_message(PCB_MSG_ERROR, "Invalid eeschema netlist header: not an export\n"); return -1; } @@ -93,7 +93,7 @@ req_subtree(nets); if ((version->children == NULL) || (strcmp(version->children->str, "D") != 0)) { - pcb_message(PCB_MSG_ERROR, "Invalid eeschema version: expected 'D', got '%s'\n", version->children->str); + rnd_message(PCB_MSG_ERROR, "Invalid eeschema version: expected 'D', got '%s'\n", version->children->str); return -1; } @@ -110,11 +110,11 @@ else if_strval(n, footprint) } if (ref == NULL) { - pcb_message(PCB_MSG_WARNING, "eeschema: ignoring component with no refdes\n"); + rnd_message(PCB_MSG_WARNING, "eeschema: ignoring component with no refdes\n"); continue; } if (footprint == NULL) { - pcb_message(PCB_MSG_WARNING, "eeschema: ignoring component %s with no footprint\n", ref); + rnd_message(PCB_MSG_WARNING, "eeschema: ignoring component %s with no footprint\n", ref); continue; } rnd_actionva(&PCB->hidlib, "ElementList", "Need", ref, footprint, value == NULL ? "" : value, NULL); @@ -154,13 +154,13 @@ netname = code; } if (netname == NULL) { - pcb_message(PCB_MSG_WARNING, "eeschema: ignoring pins of incomplete net\n"); + rnd_message(PCB_MSG_WARNING, "eeschema: ignoring pins of incomplete net\n"); continue; } /* do the binding */ if ((ref == NULL) || (pin == NULL)) { - pcb_message(PCB_MSG_WARNING, "eeschema: ignoring incomplete connection to net %s: refdes=%s pin=%s \n", netname, ref, pin); + rnd_message(PCB_MSG_WARNING, "eeschema: ignoring incomplete connection to net %s: refdes=%s pin=%s \n", netname, ref, pin); continue; } pcb_snprintf(refpin, sizeof(refpin), "%s-%s", ref, pin); @@ -186,7 +186,7 @@ fn = pcb_fopen(&PCB->hidlib, fname_net, "r"); if (fn == NULL) { - pcb_message(PCB_MSG_ERROR, "can't open file '%s' for read\n", fname_net); + rnd_message(PCB_MSG_ERROR, "can't open file '%s' for read\n", fname_net); return -1; } @@ -276,7 +276,7 @@ static int eeschema_import(pcb_plug_import_t *ctx, unsigned int aspects, const char **fns, int numfns) { if (numfns != 1) { - pcb_message(PCB_MSG_ERROR, "import_eeschema: requires exactly 1 input file name\n"); + rnd_message(PCB_MSG_ERROR, "import_eeschema: requires exactly 1 input file name\n"); return -1; } return eeschema_load(fns[0]); Index: write.c =================================================================== --- write.c (revision 30902) +++ write.c (revision 30903) @@ -51,7 +51,7 @@ typedef struct { FILE *f; /* output file */ pcb_board_t *pcb; /* board being exported */ - pcb_coord_t ox, oy; /* move every object by this origin */ + rnd_coord_t ox, oy; /* move every object by this origin */ struct { pcb_layergrp_t *grp; char name[32]; /* kicad layer name */ @@ -229,7 +229,7 @@ int skip_term; /* do not print terminals on this layer */ } klayer_t; -static void kicad_print_line(const wctx_t *ctx, const klayer_t *kly, pcb_line_t *line, int ind, pcb_coord_t dx, pcb_coord_t dy) +static void kicad_print_line(const wctx_t *ctx, const klayer_t *kly, pcb_line_t *line, int ind, rnd_coord_t dx, rnd_coord_t dy) { const char *cmd[] = {"segment", "gr_line", "fp_line"}; @@ -243,12 +243,12 @@ /* neglect (net ___ ) for now */ } -static void kicad_print_arc(const wctx_t *ctx, const klayer_t *kly, pcb_arc_t *arc, int ind, pcb_coord_t dx, pcb_coord_t dy) +static void kicad_print_arc(const wctx_t *ctx, const klayer_t *kly, pcb_arc_t *arc, int ind, rnd_coord_t dx, rnd_coord_t dy) { pcb_arc_t localArc = *arc; /* for converting ellipses to circular arcs */ /* int kicadArcShape; 3 = circle, and 2 = arc, 1= rectangle used in eeschema only */ - pcb_coord_t copperStartX, copperStartY; /* used for mapping geda copper arcs onto kicad copper lines */ - pcb_coord_t radius, xStart, yStart, xEnd, yEnd; + rnd_coord_t copperStartX, copperStartY; /* used for mapping geda copper arcs onto kicad copper lines */ + rnd_coord_t radius, xStart, yStart, xEnd, yEnd; if (arc->Width > arc->Height) { radius = arc->Height; @@ -295,20 +295,20 @@ } } -static void kicad_print_text(const wctx_t *ctx, const klayer_t *kly, pcb_text_t *text, int ind, pcb_coord_t dx, pcb_coord_t dy) +static void kicad_print_text(const wctx_t *ctx, const klayer_t *kly, pcb_text_t *text, int ind, rnd_coord_t dx, rnd_coord_t dy) { pcb_font_t *myfont = pcb_font(PCB, 0, 1); - pcb_coord_t mWidth = myfont->MaxWidth; /* kicad needs the width of the widest letter */ - pcb_coord_t defaultStrokeThickness = 100 * 2540; /* use 100 mil as default 100% stroked font line thickness */ + rnd_coord_t mWidth = myfont->MaxWidth; /* kicad needs the width of the widest letter */ + rnd_coord_t defaultStrokeThickness = 100 * 2540; /* use 100 mil as default 100% stroked font line thickness */ int kicadMirrored = 1; /* 1 is not mirrored, 0 is mirrored */ - pcb_coord_t defaultXSize; - pcb_coord_t defaultYSize; - pcb_coord_t strokeThickness; + rnd_coord_t defaultXSize; + rnd_coord_t defaultYSize; + rnd_coord_t strokeThickness; int rotation, direction; - pcb_coord_t textOffsetX; - pcb_coord_t textOffsetY; - pcb_coord_t halfStringWidth; - pcb_coord_t halfStringHeight; + rnd_coord_t textOffsetX; + rnd_coord_t textOffsetY; + rnd_coord_t halfStringWidth; + rnd_coord_t halfStringHeight; if (!(kly->lyt & PCB_LYT_COPPER) && !(kly->lyt & PCB_LYT_SILK)) { pcb_io_incompat_save(ctx->pcb->Data, (pcb_any_obj_t *)text, "text-layer", "Kicad supports text only on copper or silk - omitting text object on misc layer", NULL); @@ -400,7 +400,7 @@ fprintf(ctx->f, ")\n%*s)\n", ind, ""); } -static void kicad_print_poly_zone(const wctx_t *ctx, const klayer_t *kly, pcb_poly_t *polygon, int ind, pcb_coord_t dx, pcb_coord_t dy) +static void kicad_print_poly_zone(const wctx_t *ctx, const klayer_t *kly, pcb_poly_t *polygon, int ind, rnd_coord_t dx, rnd_coord_t dy) { int i, j; @@ -436,7 +436,7 @@ fprintf(ctx->f, "%*s)\n", ind, ""); } -static void kicad_print_poly_fp_poly(const wctx_t *ctx, const klayer_t *kly, pcb_poly_t *polygon, int ind, pcb_coord_t dx, pcb_coord_t dy) +static void kicad_print_poly_fp_poly(const wctx_t *ctx, const klayer_t *kly, pcb_poly_t *polygon, int ind, rnd_coord_t dx, rnd_coord_t dy) { int i, j; @@ -467,7 +467,7 @@ -static void kicad_print_poly(const wctx_t *ctx, const klayer_t *kly, pcb_poly_t *polygon, int ind, pcb_coord_t dx, pcb_coord_t dy, int in_module) +static void kicad_print_poly(const wctx_t *ctx, const klayer_t *kly, pcb_poly_t *polygon, int ind, rnd_coord_t dx, rnd_coord_t dy, int in_module) { if (in_module) kicad_print_poly_fp_poly(ctx, kly, polygon, ind, dx, dy); @@ -478,7 +478,7 @@ /* Print all objects of a kicad layer; if skip_term is true, ignore the objects with term ID set */ -static void kicad_print_layer(wctx_t *ctx, pcb_layer_t *ly, const klayer_t *kly, int ind, pcb_coord_t dx, pcb_coord_t dy) +static void kicad_print_layer(wctx_t *ctx, pcb_layer_t *ly, const klayer_t *kly, int ind, rnd_coord_t dx, rnd_coord_t dy) { gdl_iterator_t it; pcb_line_t *line; @@ -516,7 +516,7 @@ /* writes kicad format via data For a track segment: Position shape Xstart Ystart Xend Yend width Description layer 0 netcode timestamp status; Shape parameter is set to 0 (reserved for future) */ -static void kicad_print_pstks(wctx_t *ctx, pcb_data_t *Data, int ind, pcb_coord_t dx, pcb_coord_t dy) +static void kicad_print_pstks(wctx_t *ctx, pcb_data_t *Data, int ind, rnd_coord_t dx, rnd_coord_t dy) { gdl_iterator_t it; pcb_pstk_t *ps; @@ -524,9 +524,9 @@ padstacklist_foreach(&Data->padstack, &it, ps) { int klayer_from = 0, klayer_to = 15; - pcb_coord_t x, y, drill_dia, pad_dia, clearance, mask, x1, y1, x2, y2, thickness; + rnd_coord_t x, y, drill_dia, pad_dia, clearance, mask, x1, y1, x2, y2, thickness; pcb_pstk_compshape_t cshape; - pcb_bool plated, square, nopaste; + rnd_bool plated, square, nopaste; double psrot; if (is_subc && (ps->term == NULL)) { @@ -568,7 +568,7 @@ int n, has_mask = 0, on_bottom; pcb_pstk_proto_t *proto = pcb_pstk_get_proto_(Data, ps->proto); pcb_pstk_tshape_t *tshp = &proto->tr.array[0]; - pcb_coord_t w, h; + rnd_coord_t w, h; for(n = 0; n < tshp->len; n++) { if (tshp->shape[n].layer_mask & PCB_LYT_COPPER) { @@ -658,7 +658,7 @@ } } -void kicad_print_data(wctx_t *ctx, pcb_data_t *data, int ind, pcb_coord_t dx, pcb_coord_t dy) +void kicad_print_data(wctx_t *ctx, pcb_data_t *data, int ind, rnd_coord_t dx, rnd_coord_t dy) { int n, klayer; @@ -706,9 +706,9 @@ kicad_print_pstks(ctx, data, ind, dx, dy); } -static int kicad_print_subc(wctx_t *ctx, pcb_subc_t *subc, pcb_cardinal_t ind, pcb_coord_t dx, pcb_coord_t dy, unm_t *group1) +static int kicad_print_subc(wctx_t *ctx, pcb_subc_t *subc, pcb_cardinal_t ind, rnd_coord_t dx, rnd_coord_t dy, unm_t *group1) { - pcb_coord_t xPos, yPos, sox, soy; + rnd_coord_t xPos, yPos, sox, soy; int on_bottom; const char *currentElementName; const char *currentElementRef; @@ -804,7 +804,7 @@ } -static int kicad_print_subcs(wctx_t *ctx, pcb_data_t *Data, pcb_cardinal_t ind, pcb_coord_t dx, pcb_coord_t dy, long subc_idx) +static int kicad_print_subcs(wctx_t *ctx, pcb_data_t *Data, pcb_cardinal_t ind, rnd_coord_t dx, rnd_coord_t dy, long subc_idx) { gdl_iterator_t sit; pcb_subc_t *subc; @@ -848,7 +848,7 @@ int io_kicad_write_subcs_head(pcb_plug_io_t *ctx, void **udata, FILE *f, int lib, long num_subcs) { if ((lib) || (num_subcs > 1)) { - pcb_message(PCB_MSG_ERROR, "Can't save a library and/or multiple modules (footprints) in a single s-experssion mod file\n"); + rnd_message(PCB_MSG_ERROR, "Can't save a library and/or multiple modules (footprints) in a single s-experssion mod file\n"); return -1; } return 0; @@ -933,8 +933,8 @@ fprintf(ctx->f, "\n%*s(page A%d)\n", ind, "", paperSize); if (force_center) { - pcb_coord_t LayoutXOffset; - pcb_coord_t LayoutYOffset; + rnd_coord_t LayoutXOffset; + rnd_coord_t LayoutYOffset; /* we now sort out the offsets for centring the layout in the chosen sheet size here */ if (sheetWidth > PCB_COORD_TO_MIL(PCB->hidlib.size_x)) { /* usually A4, bigger if needed */ @@ -961,7 +961,7 @@ ctx->ox = ctx->oy = 0; } -static void kicad_print_implicit_outline(wctx_t *ctx, const char *lynam, pcb_coord_t thick, int ind) +static void kicad_print_implicit_outline(wctx_t *ctx, const char *lynam, rnd_coord_t thick, int ind) { fprintf(ctx->f, "%*s", ind, ""); pcb_fprintf(ctx->f, "(gr_line (start %.3mm %.3mm) (end %.3mm %.3mm) (layer %s) (width %.3mm))\n", @@ -1000,11 +1000,11 @@ } } - pcb_message(PCB_MSG_ERROR, "io_kicad: internal error: can not find output outline layer for drawing the implicit outline\n"); + rnd_message(PCB_MSG_ERROR, "io_kicad: internal error: can not find output outline layer for drawing the implicit outline\n"); } /* writes PCB to file in s-expression format */ -int io_kicad_write_pcb(pcb_plug_io_t *ctx, FILE *FP, const char *old_filename, const char *new_filename, pcb_bool emergency) +int io_kicad_write_pcb(pcb_plug_io_t *ctx, FILE *FP, const char *old_filename, const char *new_filename, rnd_bool emergency) { wctx_t wctx; int baseSExprIndent = 2; Index: write.h =================================================================== --- write.h (revision 30902) +++ write.h (revision 30903) @@ -30,7 +30,7 @@ #include #include "data.h" -int io_kicad_write_pcb(pcb_plug_io_t *ctx, FILE *FP, const char *old_filename, const char *new_filename, pcb_bool emergency); +int io_kicad_write_pcb(pcb_plug_io_t *ctx, FILE *FP, const char *old_filename, const char *new_filename, rnd_bool emergency); int io_kicad_write_subcs_head(pcb_plug_io_t *ctx, void **udata, FILE *f, int lib, long num_subcs); int io_kicad_write_subcs_subc(pcb_plug_io_t *ctx, void **udata, FILE *f, pcb_subc_t *subc);