Index: routest_dlg.c
===================================================================
--- routest_dlg.c	(revision 30971)
+++ routest_dlg.c	(revision 30972)
@@ -266,7 +266,7 @@
 			PCB_DAD_COORD(rstdlg_ctx.dlg, "");
 				rstdlg_ctx.wlineth = PCB_DAD_CURRENT(rstdlg_ctx.dlg);
 				PCB_DAD_HELP(rstdlg_ctx.dlg, "Thickness of line/arc objects");
-				PCB_DAD_MINMAX(rstdlg_ctx.dlg, 1, PCB_MAX_COORD);
+				PCB_DAD_MINMAX(rstdlg_ctx.dlg, 1, RND_MAX_COORD);
 				PCB_DAD_CHANGE_CB(rstdlg_ctx.dlg, rst_change_cb);
 
 			PCB_DAD_LABEL(rstdlg_ctx.dlg, "Text scale:");
@@ -273,7 +273,7 @@
 			PCB_DAD_COORD(rstdlg_ctx.dlg, "");
 				rstdlg_ctx.wtxtscale = PCB_DAD_CURRENT(rstdlg_ctx.dlg);
 				PCB_DAD_HELP(rstdlg_ctx.dlg, "Text size scale in %; 100 means normal size");
-				PCB_DAD_MINMAX(rstdlg_ctx.dlg, 1, PCB_MAX_COORD);
+				PCB_DAD_MINMAX(rstdlg_ctx.dlg, 1, RND_MAX_COORD);
 				PCB_DAD_CHANGE_CB(rstdlg_ctx.dlg, rst_change_cb);
 
 			PCB_DAD_LABEL(rstdlg_ctx.dlg, "Clearance:");
@@ -280,7 +280,7 @@
 			PCB_DAD_COORD(rstdlg_ctx.dlg, "");
 				rstdlg_ctx.wclr = PCB_DAD_CURRENT(rstdlg_ctx.dlg);
 				PCB_DAD_HELP(rstdlg_ctx.dlg, "Object clearance: any object placed with this style\nwill clear this much from sorrunding clearing-enabled polygons\n(unless the object is joined to the polygon)");
-				PCB_DAD_MINMAX(rstdlg_ctx.dlg, 1, PCB_MAX_COORD);
+				PCB_DAD_MINMAX(rstdlg_ctx.dlg, 1, RND_MAX_COORD);
 				PCB_DAD_CHANGE_CB(rstdlg_ctx.dlg, rst_change_cb);
 
 			PCB_DAD_LABEL(rstdlg_ctx.dlg, "Text thick.:");
@@ -287,7 +287,7 @@
 			PCB_DAD_COORD(rstdlg_ctx.dlg, "");
 				rstdlg_ctx.wtxtth = PCB_DAD_CURRENT(rstdlg_ctx.dlg);
 				PCB_DAD_HELP(rstdlg_ctx.dlg, "Text stroke thickness;\nif 0 use the default heuristics that\ncalculates it from text scale");
-				PCB_DAD_MINMAX(rstdlg_ctx.dlg, 1, PCB_MAX_COORD);
+				PCB_DAD_MINMAX(rstdlg_ctx.dlg, 1, RND_MAX_COORD);
 				PCB_DAD_CHANGE_CB(rstdlg_ctx.dlg, rst_change_cb);
 
 			PCB_DAD_LABEL(rstdlg_ctx.dlg, "*Via hole:");
@@ -294,7 +294,7 @@
 			PCB_DAD_COORD(rstdlg_ctx.dlg, "");
 				rstdlg_ctx.wviahole = PCB_DAD_CURRENT(rstdlg_ctx.dlg);
 				PCB_DAD_HELP(rstdlg_ctx.dlg, "Via hole diameter\nwarning: will be replaced with the padstack selector");
-				PCB_DAD_MINMAX(rstdlg_ctx.dlg, 1, PCB_MAX_COORD);
+				PCB_DAD_MINMAX(rstdlg_ctx.dlg, 1, RND_MAX_COORD);
 				PCB_DAD_CHANGE_CB(rstdlg_ctx.dlg, rst_change_cb);
 
 			PCB_DAD_LABEL(rstdlg_ctx.dlg, "*Via ring:");
@@ -301,7 +301,7 @@
 			PCB_DAD_COORD(rstdlg_ctx.dlg, "");
 				rstdlg_ctx.wviaring = PCB_DAD_CURRENT(rstdlg_ctx.dlg);
 				PCB_DAD_HELP(rstdlg_ctx.dlg, "Via ring diameter\nwarning: will be replaced with the padstack selector");
-				PCB_DAD_MINMAX(rstdlg_ctx.dlg, 1, PCB_MAX_COORD);
+				PCB_DAD_MINMAX(rstdlg_ctx.dlg, 1, RND_MAX_COORD);
 				PCB_DAD_CHANGE_CB(rstdlg_ctx.dlg, rst_change_cb);
 
 		PCB_DAD_END(rstdlg_ctx.dlg);
Index: util.c
===================================================================
--- util.c	(revision 30971)
+++ util.c	(revision 30972)
@@ -36,8 +36,8 @@
 	pcb_data_it_t it;
 	rnd_cardinal_t cnt = 0;
 
-	dst->X1 = dst->Y1 = PCB_MAX_COORD;
-	dst->X2 = dst->Y2 = -PCB_MAX_COORD;
+	dst->X1 = dst->Y1 = RND_MAX_COORD;
+	dst->X2 = dst->Y2 = -RND_MAX_COORD;
 
 	for(o = pcb_data_first(&it, (pcb_data_t *)data, PCB_OBJ_CLASS_REAL); o != NULL; o = pcb_data_next(&it)) {
 		if (!PCB_FLAG_TEST(flg, o))