Index: write.c
===================================================================
--- write.c	(revision 31006)
+++ write.c	(revision 31007)
@@ -93,11 +93,11 @@
 				continue;
 			}
 
-			pcb_fprintf(FP, "Po 3 %.0mk %.0mk %.0mk %.0mk %.0mk\n", /* testing kicad printf */
+			rnd_fprintf(FP, "Po 3 %.0mk %.0mk %.0mk %.0mk %.0mk\n", /* testing kicad printf */
 				x + xOffset, y + yOffset, x + xOffset, y + yOffset, pad_dia);
 TODO(": check if drill_dia can be applied")
 TODO(": bbvia")
-			pcb_fprintf(FP, "De 15 1 0 0 0\n"); /* this is equivalent to 0F, via from 15 -> 0 */
+			rnd_fprintf(FP, "De 15 1 0 0 0\n"); /* this is equivalent to 0F, via from 15 -> 0 */
 		}
 	}
 	return 0;
@@ -107,7 +107,7 @@
 static int write_kicad_legacy_layout_via_drill_size(FILE *FP)
 {
 TODO(": do not hardwire this")
-	pcb_fprintf(FP, "ViaDrill 250\n"); /* decimil format, default for now, ~= 0.635mm */
+	rnd_fprintf(FP, "ViaDrill 250\n"); /* decimil format, default for now, ~= 0.635mm */
 	return 0;
 }
 
@@ -122,13 +122,13 @@
 		int localFlag = 0;
 		linelist_foreach(&layer->Line, &it, line) {
 			if (currentLayer < 16) { /* a copper line i.e. track */
-				pcb_fprintf(FP, "Po 0 %.0mk %.0mk %.0mk %.0mk %.0mk\n", line->Point1.X + xOffset, line->Point1.Y + yOffset, line->Point2.X + xOffset, line->Point2.Y + yOffset, line->Thickness);
-				pcb_fprintf(FP, "De %d 0 0 0 0\n", currentLayer); /* omitting net info */
+				rnd_fprintf(FP, "Po 0 %.0mk %.0mk %.0mk %.0mk %.0mk\n", line->Point1.X + xOffset, line->Point1.Y + yOffset, line->Point2.X + xOffset, line->Point2.Y + yOffset, line->Thickness);
+				rnd_fprintf(FP, "De %d 0 0 0 0\n", currentLayer); /* omitting net info */
 			}
 			else if ((currentLayer == 20) || (currentLayer == 21) || (currentLayer == 28)) { /* a silk line or outline */
 				fputs("$DRAWSEGMENT\n", FP);
-				pcb_fprintf(FP, "Po 0 %.0mk %.0mk %.0mk %.0mk %.0mk\n", line->Point1.X + xOffset, line->Point1.Y + yOffset, line->Point2.X + xOffset, line->Point2.Y + yOffset, line->Thickness);
-				pcb_fprintf(FP, "De %d 0 0 0 0\n", currentLayer); /* omitting net info */
+				rnd_fprintf(FP, "Po 0 %.0mk %.0mk %.0mk %.0mk %.0mk\n", line->Point1.X + xOffset, line->Point1.Y + yOffset, line->Point2.X + xOffset, line->Point2.Y + yOffset, line->Thickness);
+				rnd_fprintf(FP, "De %d 0 0 0 0\n", currentLayer); /* omitting net info */
 				fputs("$EndDRAWSEGMENT\n", FP);
 			}
 			localFlag |= 1;
@@ -182,13 +182,13 @@
 
 			if (currentLayer < 16) { /* a copper arc, i.e. track, is unsupported by kicad, and will be exported as a line */
 				kicadArcShape = 0; /* make it a line for copper layers - kicad doesn't do arcs on copper */
-				pcb_fprintf(FP, "Po %d %.0mk %.0mk %.0mk %.0mk %.0mk\n", kicadArcShape, copperStartX, copperStartY, xEnd, yEnd, arc->Thickness);
-				pcb_fprintf(FP, "De %d 0 0 0 0\n", currentLayer); /* in theory, copper arcs unsupported by kicad, make angle = 0 */
+				rnd_fprintf(FP, "Po %d %.0mk %.0mk %.0mk %.0mk %.0mk\n", kicadArcShape, copperStartX, copperStartY, xEnd, yEnd, arc->Thickness);
+				rnd_fprintf(FP, "De %d 0 0 0 0\n", currentLayer); /* in theory, copper arcs unsupported by kicad, make angle = 0 */
 			}
 			else if ((currentLayer == 20) || (currentLayer == 21) || (currentLayer == 28)) { /* a silk arc or outline */
 				fputs("$DRAWSEGMENT\n", FP);
-				pcb_fprintf(FP, "Po %d %.0mk %.0mk %.0mk %.0mk %.0mk\n", kicadArcShape, xStart, yStart, xEnd, yEnd, arc->Thickness);
-				pcb_fprintf(FP, "De %d 0 %mA 0 0\n", currentLayer, arc->Delta); /* in theory, decidegrees != 900 unsupported by older kicad */
+				rnd_fprintf(FP, "Po %d %.0mk %.0mk %.0mk %.0mk %.0mk\n", kicadArcShape, xStart, yStart, xEnd, yEnd, arc->Thickness);
+				rnd_fprintf(FP, "De %d 0 %mA 0 0\n", currentLayer, arc->Delta); /* in theory, decidegrees != 900 unsupported by older kicad */
 				fputs("$EndDRAWSEGMENT\n", FP);
 			}
 			localFlag |= 1;
@@ -302,8 +302,8 @@
 					}
 					textOffsetX = halfStringWidth;
 				}
-				pcb_fprintf(FP, "Po %.0mk %.0mk %.0mk %.0mk %.0mk %d\n", text->X + xOffset + textOffsetX, text->Y + yOffset + textOffsetY, defaultXSize, defaultYSize, strokeThickness, rotation);
-				pcb_fprintf(FP, "De %d %d B98C Normal\n", currentLayer, kicadMirrored); /* timestamp made up B98C  */
+				rnd_fprintf(FP, "Po %.0mk %.0mk %.0mk %.0mk %.0mk %d\n", text->X + xOffset + textOffsetX, text->Y + yOffset + textOffsetY, defaultXSize, defaultYSize, strokeThickness, rotation);
+				rnd_fprintf(FP, "De %d %d B98C Normal\n", currentLayer, kicadMirrored); /* timestamp made up B98C  */
 				fputs("$EndTEXTPCB\n", FP);
 			}
 			localFlag |= 1;
@@ -392,7 +392,7 @@
 
 	fprintf(FP, "$MODULE %s\n", uname);
 TODO(": do not hardwire time stamps")
-	pcb_fprintf(FP, "Po %.0mk %.0mk 0 %d 51534DFF 00000000 ~~\n", ox, oy, copperLayer);
+	rnd_fprintf(FP, "Po %.0mk %.0mk 0 %d 51534DFF 00000000 ~~\n", ox, oy, copperLayer);
 	fprintf(FP, "Li %s\n", uname); /* This needs to be unique */
 	fprintf(FP, "Cd %s\n", uname);
 	fputs("Sc 0\n", FP);
@@ -424,7 +424,7 @@
 
 		if (pcb_pstk_export_compat_via(ps, &x, &y, &drill_dia, &pad_dia, &clearance, &mask, &cshape, &plated)) {
 			fputs("$PAD\n", FP);
-			pcb_fprintf(FP, "Po %.0mk %.0mk\n", x - sox, y - soy);  /* positions of pad */
+			rnd_fprintf(FP, "Po %.0mk %.0mk\n", x - sox, y - soy);  /* positions of pad */
 			fputs("Sh ", FP); /* pin shape descriptor */
 			pcb_print_quoted_string(FP, (char *)RND_EMPTY(ps->term));
 
@@ -434,11 +434,11 @@
 				pcb_io_incompat_save(subc->data, (pcb_any_obj_t *)ps, "padstack-shape", "can't export shaped pin; needs to be square or circular - using circular instead", NULL);
 				fputs(" C ", FP);
 			}
-			pcb_fprintf(FP, "%.0mk %.0mk ", pad_dia, pad_dia); /* height = width */
+			rnd_fprintf(FP, "%.0mk %.0mk ", pad_dia, pad_dia); /* height = width */
 			fprintf(FP, "0 0 %d\n", (int)(psrot * 10)); /* deltaX deltaY Orientation as float in decidegrees */
 
 			/* drill details; size and x,y pos relative to pad location */
-			pcb_fprintf(FP, "Dr %.0mk 0 0\n", drill_dia);
+			rnd_fprintf(FP, "Dr %.0mk 0 0\n", drill_dia);
 
 			fputs("At STD N 00E0FFFF\n", FP); /* through hole STD pin, all copper layers */
 
@@ -515,13 +515,13 @@
 				if (tshp->shape[n].layer_mask & PCB_LYT_MASK)
 					has_mask = 1;
 			}
-			pcb_fprintf(FP, "Po %.0mk %.0mk\n", ps->x + cx - sox, ps->y + cy - soy);  /* positions of pad */
+			rnd_fprintf(FP, "Po %.0mk %.0mk\n", ps->x + cx - sox, ps->y + cy - soy);  /* positions of pad */
 
 			fputs("Sh ", FP); /* pin shape descriptor */
 			pcb_print_quoted_string(FP, (char *)RND_EMPTY(ps->term));
-			pcb_fprintf(FP, " %c %.0mk %.0mk ", shape_chr, w, h);
+			rnd_fprintf(FP, " %c %.0mk %.0mk ", shape_chr, w, h);
 
-			pcb_fprintf(FP, "0 0 %d\n", (int)(psrot*10.0)); /* deltaX deltaY Orientation as float in decidegrees */
+			rnd_fprintf(FP, "0 0 %d\n", (int)(psrot*10.0)); /* deltaX deltaY Orientation as float in decidegrees */
 
 			fputs("Dr 0 0 0\n", FP); /* drill details; zero size; x,y pos vs pad location */
 
@@ -567,7 +567,7 @@
 		silkLayer = (lyt & PCB_LYT_BOTTOM) ? 20 : 21;
 
 		linelist_foreach(&ly->Line, &it, line) {
-			pcb_fprintf(FP, "DS %.0mk %.0mk %.0mk %.0mk %.0mk ",
+			rnd_fprintf(FP, "DS %.0mk %.0mk %.0mk %.0mk %.0mk ",
 				line->Point1.X - sox, line->Point1.Y - soy,
 				line->Point2.X - sox, line->Point2.Y - soy,
 				line->Thickness);
@@ -579,13 +579,13 @@
 			pcb_arc_get_end(arc, 1, &arcEndX, &arcEndY);
 
 			if ((arc->Delta == 360.0) || (arc->Delta == -360.0)) { /* it's a circle */
-				pcb_fprintf(FP, "DC %.0mk %.0mk %.0mk %.0mk %.0mk ",
+				rnd_fprintf(FP, "DC %.0mk %.0mk %.0mk %.0mk %.0mk ",
 					arc->X - sox, arc->Y - soy, /* centre */
 					arcStartX - sox, arcStartY - soy, /* on circle */
 					arc->Thickness);
 			}
 			else {
-				pcb_fprintf(FP, "DA %.0mk %.0mk %.0mk %.0mk %mA %.0mk ",
+				rnd_fprintf(FP, "DA %.0mk %.0mk %.0mk %.0mk %mA %.0mk ",
 					arc->X - sox, arc->Y - soy, /* centre */
 					arcEndX - sox, arcEndY - soy,
 					arc->Delta, /* CW delta angle in decidegrees */
@@ -647,7 +647,7 @@
 					if (i == (polygon->PointN - 1)) {
 						j = 1; /* flags that this is the last vertex of the outline */
 					}
-					pcb_fprintf(FP, "ZCorner %.0mk %.0mk %d\n", polygon->Points[i].X + xOffset, polygon->Points[i].Y + yOffset, j);
+					rnd_fprintf(FP, "ZCorner %.0mk %.0mk %d\n", polygon->Points[i].X + xOffset, polygon->Points[i].Y + yOffset, j);
 				}
 
 				/* in here could go additional plolygon descriptors for holes removed from  the previously defined outer polygon */
@@ -775,7 +775,7 @@
 		LayoutXOffset = PCB_MIL_TO_COORD(sheetWidth) / 2 - PCB->hidlib.size_x / 2;
 	}
 	else { /* the layout is bigger than A0; most unlikely, but... */
-		pcb_fprintf(FP, "%.0ml ", PCB->hidlib.size_x);
+		rnd_fprintf(FP, "%.0ml ", PCB->hidlib.size_x);
 		LayoutXOffset = 0;
 	}
 	if (sheetHeight > PCB_COORD_TO_MIL(PCB->hidlib.size_y)) {
@@ -783,7 +783,7 @@
 		LayoutYOffset = PCB_MIL_TO_COORD(sheetHeight) / 2 - PCB->hidlib.size_y / 2;
 	}
 	else { /* the layout is bigger than A0; most unlikely, but... */
-		pcb_fprintf(FP, "%.0ml", PCB->hidlib.size_y);
+		rnd_fprintf(FP, "%.0ml", PCB->hidlib.size_y);
 		LayoutYOffset = 0;
 	}
 	fputs("\n", FP);
@@ -894,20 +894,20 @@
 	}
 	else { /* no outline layer per se, export the board margins instead  - obviously some scope to reduce redundant code... */
 		fputs("$DRAWSEGMENT\n", FP);
-		pcb_fprintf(FP, "Po 0 %.0mk %.0mk %.0mk %.0mk %.0mk\n", PCB->hidlib.size_x / 2 - LayoutXOffset, PCB->hidlib.size_y / 2 - LayoutYOffset, PCB->hidlib.size_x / 2 + LayoutXOffset, PCB->hidlib.size_y / 2 - LayoutYOffset, outlineThickness);
-		pcb_fprintf(FP, "De %d 0 0 0 0\n", currentKicadLayer);
+		rnd_fprintf(FP, "Po 0 %.0mk %.0mk %.0mk %.0mk %.0mk\n", PCB->hidlib.size_x / 2 - LayoutXOffset, PCB->hidlib.size_y / 2 - LayoutYOffset, PCB->hidlib.size_x / 2 + LayoutXOffset, PCB->hidlib.size_y / 2 - LayoutYOffset, outlineThickness);
+		rnd_fprintf(FP, "De %d 0 0 0 0\n", currentKicadLayer);
 		fputs("$EndDRAWSEGMENT\n", FP);
 		fputs("$DRAWSEGMENT\n", FP);
-		pcb_fprintf(FP, "Po 0 %.0mk %.0mk %.0mk %.0mk %.0mk\n", PCB->hidlib.size_x / 2 + LayoutXOffset, PCB->hidlib.size_y / 2 - LayoutYOffset, PCB->hidlib.size_x / 2 + LayoutXOffset, PCB->hidlib.size_y / 2 + LayoutYOffset, outlineThickness);
-		pcb_fprintf(FP, "De %d 0 0 0 0\n", currentKicadLayer);
+		rnd_fprintf(FP, "Po 0 %.0mk %.0mk %.0mk %.0mk %.0mk\n", PCB->hidlib.size_x / 2 + LayoutXOffset, PCB->hidlib.size_y / 2 - LayoutYOffset, PCB->hidlib.size_x / 2 + LayoutXOffset, PCB->hidlib.size_y / 2 + LayoutYOffset, outlineThickness);
+		rnd_fprintf(FP, "De %d 0 0 0 0\n", currentKicadLayer);
 		fputs("$EndDRAWSEGMENT\n", FP);
 		fputs("$DRAWSEGMENT\n", FP);
-		pcb_fprintf(FP, "Po 0 %.0mk %.0mk %.0mk %.0mk %.0mk\n", PCB->hidlib.size_x / 2 + LayoutXOffset, PCB->hidlib.size_y / 2 + LayoutYOffset, PCB->hidlib.size_x / 2 - LayoutXOffset, PCB->hidlib.size_y / 2 + LayoutYOffset, outlineThickness);
-		pcb_fprintf(FP, "De %d 0 0 0 0\n", currentKicadLayer);
+		rnd_fprintf(FP, "Po 0 %.0mk %.0mk %.0mk %.0mk %.0mk\n", PCB->hidlib.size_x / 2 + LayoutXOffset, PCB->hidlib.size_y / 2 + LayoutYOffset, PCB->hidlib.size_x / 2 - LayoutXOffset, PCB->hidlib.size_y / 2 + LayoutYOffset, outlineThickness);
+		rnd_fprintf(FP, "De %d 0 0 0 0\n", currentKicadLayer);
 		fputs("$EndDRAWSEGMENT\n", FP);
 		fputs("$DRAWSEGMENT\n", FP);
-		pcb_fprintf(FP, "Po 0 %.0mk %.0mk %.0mk %.0mk %.0mk\n", PCB->hidlib.size_x / 2 - LayoutXOffset, PCB->hidlib.size_y / 2 + LayoutYOffset, PCB->hidlib.size_x / 2 - LayoutXOffset, PCB->hidlib.size_y / 2 - LayoutYOffset, outlineThickness);
-		pcb_fprintf(FP, "De %d 0 0 0 0\n", currentKicadLayer);
+		rnd_fprintf(FP, "Po 0 %.0mk %.0mk %.0mk %.0mk %.0mk\n", PCB->hidlib.size_x / 2 - LayoutXOffset, PCB->hidlib.size_y / 2 + LayoutYOffset, PCB->hidlib.size_x / 2 - LayoutXOffset, PCB->hidlib.size_y / 2 - LayoutYOffset, outlineThickness);
+		rnd_fprintf(FP, "De %d 0 0 0 0\n", currentKicadLayer);
 		fputs("$EndDRAWSEGMENT\n", FP);
 	}