Index: trunk/src_plugins/export_openems/export_openems.c
===================================================================
--- trunk/src_plugins/export_openems/export_openems.c (revision 31994)
+++ trunk/src_plugins/export_openems/export_openems.c (revision 31995)
@@ -86,6 +86,9 @@
unsigned warn_subc_term:1;
unsigned warn_port_pstk:1;
unsigned fmt_matlab:1; /* when 1, use matlab syntax; 0 means xml syntax */
+
+ /* xml */
+ unsigned cond_sheet_open:1;
} wctx_t;
static FILE *f = NULL;
@@ -711,6 +714,8 @@
{
if (flags & PCB_LYT_COPPER) { /* export copper layers only */
ems_ctx->clayer = ems_ctx->lg_pcb2ems[group];
+ if ((!ems_ctx->fmt_matlab) && (!is_empty))
+ openems_wr_xml_layergrp_begin(ems_ctx, &ems_ctx->pcb->LayerGroups.grp[group]);
return 1;
}
return 0;
Index: trunk/src_plugins/export_openems/openems_xml.c
===================================================================
--- trunk/src_plugins/export_openems/openems_xml.c (revision 31994)
+++ trunk/src_plugins/export_openems/openems_xml.c (revision 31995)
@@ -28,13 +28,22 @@
static double def_end_crit = 1e-05;
static long def_f_max = 2100000000;
-static void openems_wr_xml_grp_copper(wctx_t *ctx, pcb_layergrp_t *g)
+static void openems_wr_xml_layergrp_end(wctx_t *ctx)
{
-TODO("Fix hardwired constants");
+ if (ctx->cond_sheet_open) {
+ fprintf(ctx->f, " \n");
+ fprintf(ctx->f, " \n");
+ ctx->cond_sheet_open = 0;
+ }
+
+}
+
+static void openems_wr_xml_layergrp_begin(wctx_t *ctx, pcb_layergrp_t *g)
+{
+ openems_wr_xml_layergrp_end(ctx);
fprintf(ctx->f, " \n", g->name);
fprintf(ctx->f, " \n");
- fprintf(ctx->f, " \n");
- fprintf(ctx->f, " \n");
+ ctx->cond_sheet_open = 1;
}
static void openems_wr_xml_grp_substrate(wctx_t *ctx, pcb_layergrp_t *g)
@@ -52,13 +61,6 @@
rnd_cardinal_t gid;
fprintf(ctx->f, " \n");
- for(gid = 0; gid < ctx->pcb->LayerGroups.len; gid++) {
- pcb_layergrp_t *g = &ctx->pcb->LayerGroups.grp[gid];
- if (g->ltype & PCB_LYT_COPPER)
- openems_wr_xml_grp_copper(ctx, g);
- else if (g->ltype & PCB_LYT_SUBSTRATE)
- openems_wr_xml_grp_substrate(ctx, g);
- }
ectx.view.X1 = 0;
ectx.view.Y1 = 0;
@@ -66,7 +68,16 @@
ectx.view.Y2 = ctx->pcb->hidlib.size_y;
rnd_expose_main(&openems_hid, &ectx, NULL);
+ openems_wr_xml_layergrp_end(ctx);
+ /* export substrate bricks */
+ for(gid = 0; gid < ctx->pcb->LayerGroups.len; gid++) {
+ pcb_layergrp_t *g = &ctx->pcb->LayerGroups.grp[gid];
+ if (g->ltype & PCB_LYT_SUBSTRATE)
+ openems_wr_xml_grp_substrate(ctx, g);
+ }
+
+
fprintf(ctx->f, " \n");
}