Index: trunk/src_plugins/export_openems/export_openems.c =================================================================== --- trunk/src_plugins/export_openems/export_openems.c (revision 31999) +++ trunk/src_plugins/export_openems/export_openems.c (revision 32000) @@ -61,7 +61,8 @@ #define MESH_NAME "openems" -#define PRIO_COPPER 1 +#define PRIO_SUBSTRATE 1 +#define PRIO_COPPER 2 typedef struct rnd_hid_gc_s { rnd_core_gc_t core_gc; Index: trunk/src_plugins/export_openems/openems_xml.c =================================================================== --- trunk/src_plugins/export_openems/openems_xml.c (revision 31999) +++ trunk/src_plugins/export_openems/openems_xml.c (revision 32000) @@ -35,17 +35,30 @@ fprintf(ctx->f, " \n"); ctx->cond_sheet_open = 0; } +} +static rnd_coord_t get_grp_elev(wctx_t *ctx, pcb_layergrp_t *g) +{ + rnd_layergrp_id_t from, to; + + if (pcb_layergrp_list(ctx->pcb, PCB_LYT_BOTTOM|PCB_LYT_COPPER, &from, 1) != 1) { + ctx->elevation = 0; + rnd_message(RND_MSG_ERROR, "Missing bottom copper layer group - can not simulate\n"); + return -1; + } + to = g - ctx->pcb->LayerGroups.grp; + if (from == to) + return 0; + return pcb_stack_thickness(ctx->pcb, "openems", PCB_BRDTHICK_PRINT_ERROR, from, 1, to, 0, PCB_LYT_SUBSTRATE|PCB_LYT_COPPER); } static void openems_wr_xml_layergrp_begin(wctx_t *ctx, pcb_layergrp_t *g) { - rnd_layergrp_id_t from, to; - - openems_wr_xml_layergrp_end(ctx); rnd_coord_t th; pcb_layer_t *ly = NULL; + openems_wr_xml_layergrp_end(ctx); + if (g->len < 0) { /* shouldn't happen: we are not called for empty layer groups */ return; @@ -61,24 +74,68 @@ fprintf(ctx->f, " \n"); ctx->cond_sheet_open = 1; - - if (pcb_layergrp_list(ctx->pcb, PCB_LYT_BOTTOM|PCB_LYT_COPPER, &from, 1) != 1) { - ctx->elevation = 0; - rnd_message(RND_MSG_ERROR, "Missing bottom copper layer group - can not simulate\n"); - TODO("return error"); - } - to = g - ctx->pcb->LayerGroups.grp; - th = pcb_stack_thickness(ctx->pcb, "openems", PCB_BRDTHICK_PRINT_ERROR, from, 1, to, 0, PCB_LYT_SUBSTRATE|PCB_LYT_COPPER); + th = get_grp_elev(ctx, g); TODO("check for -1 and return error"); ctx->elevation = RND_COORD_TO_MM(th); } +TODO("remove this once the function is moved and published in core") +extern const char *pcb_layergrp_thickness_attr(pcb_layergrp_t *grp, const char *namespace); + +static int openems_wr_xml_outline(wctx_t *ctx, pcb_layergrp_t *g) +{ + int n; + pcb_any_obj_t *out1; + const char *s; + rnd_coord_t th = 0; + + s = pcb_layergrp_thickness_attr(g, "openems"); + if (s != NULL) + th = rnd_get_value(s, NULL, NULL, NULL); + + if (th <= 0) { + rnd_message(RND_MSG_ERROR, "Substrate thickness is missing or invalid - can't export\n"); + return -1; + } + +TODO("layer: consider multiple outline layers instead") + out1 = pcb_topoly_find_1st_outline(ctx->pcb); + + rnd_fprintf(ctx->f, " \n", PRIO_SUBSTRATE, ctx->elevation, th); + if (out1 != NULL) { + long n; + pcb_poly_t *p = pcb_topoly_conn(ctx->pcb, out1, PCB_TOPOLY_KEEP_ORIG | PCB_TOPOLY_FLOATING); + + for(n = 0; n < p->PointN; n++) + rnd_fprintf(ctx->f, " \n", p->Points[n].X, -p->Points[n].Y); + pcb_poly_free(p); + } + else { + /* rectangular board size */ + rnd_fprintf(ctx->f, " \n", 0, 0); + rnd_fprintf(ctx->f, " \n", ctx->pcb->hidlib.size_x, 0); + rnd_fprintf(ctx->f, " \n", ctx->pcb->hidlib.size_x, -ctx->pcb->hidlib.size_y); + rnd_fprintf(ctx->f, " \n", 0, -ctx->pcb->hidlib.size_y); + } + rnd_fprintf(ctx->f, " \n"); + return 0; +} + + static void openems_wr_xml_grp_substrate(wctx_t *ctx, pcb_layergrp_t *g) { + rnd_coord_t th = get_grp_elev(ctx, g); +TODO("check for -1 and return error"); + ctx->elevation = RND_COORD_TO_MM(th); + TODO("Fix hardwired constants"); fprintf(ctx->f, " \n", g->name); - fprintf(ctx->f, " "); - fprintf(ctx->f, " "); + fprintf(ctx->f, " \n"); + fprintf(ctx->f, " \n"); + fprintf(ctx->f, " \n"); + fprintf(ctx->f, " \n"); + openems_wr_xml_outline(ctx, g); + fprintf(ctx->f, " \n"); fprintf(ctx->f, " \n"); }