Index: trunk/src/obj_pstk_inlines.h
===================================================================
--- trunk/src/obj_pstk_inlines.h	(revision 32748)
+++ trunk/src/obj_pstk_inlines.h	(revision 32749)
@@ -352,7 +352,10 @@
 	if (proto->mech_idx < 0)
 		return NULL; /* no mech shape -> no slot */
 
-	ts = pcb_pstk_get_tshape(ps);
+	if (ps == NULL)
+		ts = &proto->tr.array[0];
+	else
+		ts = pcb_pstk_get_tshape(ps);
 	return ts->shape + proto->mech_idx;
 }
 
Index: trunk/src/obj_pstk_proto.c
===================================================================
--- trunk/src/obj_pstk_proto.c	(revision 32748)
+++ trunk/src/obj_pstk_proto.c	(revision 32749)
@@ -65,6 +65,7 @@
 
 void pcb_pstk_proto_update(pcb_pstk_proto_t *dst)
 {
+	static const pcb_pstk_t dummy_ps = {0};
 	pcb_pstk_tshape_t *ts = &dst->tr.array[0];
 	unsigned int n;
 
@@ -72,6 +73,8 @@
 	dst->mech_idx = -1;
 
 	if (ts != NULL) {
+		pcb_pstk_shape_t *hole, holetmp;
+
 		/* find and cache the index of the mech shape (slot) */
 		for(n = 0; n < ts->len; n++) {
 			if (ts->shape[n].layer_mask & PCB_LYT_MECH) {
@@ -80,8 +83,16 @@
 			}
 		}
 
-		/* mark each copper shape with whether it overlaps with the hole/mech shape or not */
+/*rnd_trace("pstk_upd:\n");*/
+
+		/* mark each shape with whether it overlaps with the hole/mech shape or not */
+		hole = pcb_pstk_shape_mech_or_hole_(NULL, dst, &holetmp);
 		for(n = 0; n < ts->len; n++) {
+			if (hole != NULL)
+				ts->shape[n].hconn = pcb_pstk_shape_intersect(&dummy_ps, &ts->shape[n], &dummy_ps, hole);
+			else
+				ts->shape[n].hconn = 0;
+/*rnd_trace(" [%d]: %d\n", n, ts->shape[n].hconn);*/
 		}
 	}
 }
Index: trunk/src/obj_pstk_shape.h
===================================================================
--- trunk/src/obj_pstk_shape.h	(revision 32748)
+++ trunk/src/obj_pstk_shape.h	(revision 32749)
@@ -64,7 +64,7 @@
 		PCB_PSSH_HSHADOW             /* for clearance: pretend the shape is the same as the drill's or slot's; but do not add anything positive to the target layer */
 	} shape;
 	rnd_coord_t clearance;         /* per layer clearance: internal layer clearance is sometimes different for production or insulation reasons (IPC2221A) */
-	unsigned hconn:1;              /* shape is connected to hole/slot; this is abstract, it ignores plating and bbvia aspects */
+	unsigned hconn:1;              /* shape is connected to hole/slot; this is abstract, it ignores plating and bbvia aspects; valid only in the non-transformed proto, tr[0] */
 } pcb_pstk_shape_t;
 
 /* transformed prototype */