Index: trunk/src_plugins/io_pcb/file.c
===================================================================
--- trunk/src_plugins/io_pcb/file.c	(revision 34425)
+++ trunk/src_plugins/io_pcb/file.c	(revision 34426)
@@ -309,17 +309,11 @@
 
 	if (vtroutestyle_len(&PCB->RouteStyle) > 0) {
 		for (group = 0; group < vtroutestyle_len(&PCB->RouteStyle) - 1; group++) {
-			if (pcb_brave & PCB_BRAVE_LIHATA_V8) {
-				rnd_coord_t drill_dia, pad_dia, mask;
-				pcb_compat_route_style_via_save(PCB->Data, &PCB->RouteStyle.array[group], &drill_dia, &pad_dia, &mask);
-				rnd_fprintf(FP, "%s,%[0],%[0],%[0],%[0]:", PCB->RouteStyle.array[group].name,
-					PCB->RouteStyle.array[group].Thick, PCB->RouteStyle.array[group].Diameter,
-					PCB->RouteStyle.array[group].Hole, PCB->RouteStyle.array[group].Clearance);
-			}
-			else /* TODO("pstk #21: remove this branch") */
-				rnd_fprintf(FP, "%s,%[0],%[0],%[0],%[0]:", PCB->RouteStyle.array[group].name,
-					PCB->RouteStyle.array[group].Thick, PCB->RouteStyle.array[group].Diameter,
-					PCB->RouteStyle.array[group].Hole, PCB->RouteStyle.array[group].Clearance);
+			rnd_coord_t drill_dia, pad_dia, mask;
+			pcb_compat_route_style_via_save(PCB->Data, &PCB->RouteStyle.array[group], &drill_dia, &pad_dia, &mask);
+			rnd_fprintf(FP, "%s,%[0],%[0],%[0],%[0]:", PCB->RouteStyle.array[group].name,
+				PCB->RouteStyle.array[group].Thick, PCB->RouteStyle.array[group].Diameter,
+				PCB->RouteStyle.array[group].Hole, PCB->RouteStyle.array[group].Clearance);
 		}
 		rnd_fprintf(FP, "%s,%[0],%[0],%[0],%[0]\"]\n\n", PCB->RouteStyle.array[group].name,
 								PCB->RouteStyle.array[group].Thick,
Index: trunk/src_plugins/io_pcb/rst_parse.c
===================================================================
--- trunk/src_plugins/io_pcb/rst_parse.c	(revision 34425)
+++ trunk/src_plugins/io_pcb/rst_parse.c	(revision 34426)
@@ -103,15 +103,8 @@
 			s++;
 	}
 
-	if (pcb_brave & PCB_BRAVE_LIHATA_V8) {
-		if (pcb_compat_route_style_via_load(data, routeStyle, hole_dia, pad_dia, mask) != 0)
-			rnd_message(RND_MSG_WARNING, "Route style '%s': falied to create via padstack prototype\n", routeStyle->name);
-	}
-	else {
-TODO("pstk #21: remove this branch");
-		routeStyle->Diameter = pad_dia;
-		routeStyle->Hole = hole_dia;
-	}
+	if (pcb_compat_route_style_via_load(data, routeStyle, hole_dia, pad_dia, mask) != 0)
+		rnd_message(RND_MSG_WARNING, "Route style '%s': falied to create via padstack prototype\n", routeStyle->name);
 
 	*str = s;
 	return 0;