Index: tool_line.c
===================================================================
--- tool_line.c	(revision 34426)
+++ tool_line.c	(revision 34427)
@@ -56,12 +56,8 @@
 #include "obj_rat_draw.h"
 #include "route_draw.h"
 
-TODO("pstk #21: remove this when via is removed and the padstack is created from style directly")
-#include "src_plugins/lib_compat_help/pstk_compat.h"
-
 static pcb_layer_t *last_layer;
 
-
 void pcb_tool_line_init(void)
 {
 	rnd_hid_notify_crosshair_change(&PCB->hidlib, rnd_false);
@@ -189,7 +185,6 @@
 		/* place a via if vias are visible, the layer is
 			 in a new group since the last line and there
 			 isn't a pin already here */
-TODO("pstk #21: do not work in comp mode, use a pstk proto - scconfig also has TODO #21, fix it there too")
 		if (conf_core.editor.auto_via && pcb->pstk_on
 				&& pcb_layer_get_group_(PCB_CURRLAYER(pcb)) != pcb_layer_get_group_(last_layer)
 				&& pcb_search_obj_by_location(PCB_OBJ_CLASS_PIN, &ptr1, &ptr2, &ptr3,
@@ -200,11 +195,7 @@
 				&& (pcb_layer_flags_(PCB_CURRLAYER(pcb)) & PCB_LYT_COPPER)
 				&& (pcb_layer_flags_(last_layer) & PCB_LYT_COPPER)
 				&& (!pcb->is_footprint)
-				&& ((ps = pcb_pstk_new_compat_via(pcb->Data, -1,
-															pcb_crosshair.AttachedLine.Point1.X,
-															pcb_crosshair.AttachedLine.Point1.Y,
-				conf_core.design.via_drilling_hole, conf_core.design.via_thickness, conf_core.design.clearance,
-			0, PCB_PSTK_COMPAT_ROUND, rnd_true)) != NULL)) {
+				&& ((ps = pcb_pstk_new(pcb->Data, -1, conf_core.design.via_proto, pcb_crosshair.AttachedLine.Point1.X, pcb_crosshair.AttachedLine.Point1.Y, conf_core.design.clearance, pcb_flag_make(PCB_FLAG_CLEARLINE))) != NULL)) {
 					pcb_obj_add_attribs((pcb_any_obj_t *)ps, pcb->pen_attr, NULL);
 					pcb_undo_add_obj_to_create(PCB_OBJ_PSTK, ps, ps, ps);
 		}
@@ -282,7 +273,6 @@
 			/* place a via if vias are visible, the layer is
 				 in a new group since the last line and there
 				 isn't a pin already here */
-TODO("pstk #21: do not work in comp mode, use a pstk proto - scconfig also has TODO #21, fix it there too")
 			if (pcb->pstk_on
 					&& pcb_layer_get_group_(PCB_CURRLAYER(pcb)) != pcb_layer_get_group_(last_layer) 
 					&& (pcb_layer_flags_(PCB_CURRLAYER(pcb)) & PCB_LYT_COPPER)
@@ -292,11 +282,7 @@
 																 pcb_crosshair.AttachedLine.Point1.X,
 																 pcb_crosshair.AttachedLine.Point1.Y,
 																 conf_core.design.via_thickness / 2) == PCB_OBJ_VOID
-				&& ((ps = pcb_pstk_new_compat_via(pcb->Data, -1,
-															pcb_crosshair.AttachedLine.Point1.X,
-															pcb_crosshair.AttachedLine.Point1.Y,
-															conf_core.design.via_drilling_hole, conf_core.design.via_thickness, conf_core.design.clearance,
-															0, PCB_PSTK_COMPAT_ROUND, rnd_true)) != NULL)) {
+					&& ((ps = pcb_pstk_new(pcb->Data, -1, conf_core.design.via_proto, pcb_crosshair.AttachedLine.Point1.X, pcb_crosshair.AttachedLine.Point1.Y, conf_core.design.clearance, pcb_flag_make(PCB_FLAG_CLEARLINE))) != NULL)) {
 				pcb_obj_add_attribs((pcb_any_obj_t *)ps, pcb->pen_attr, NULL);
 				pcb_undo_add_obj_to_create(PCB_OBJ_PSTK, ps, ps, ps);
 				pcb_pstk_invalidate_draw(ps);
Index: tool_via.c
===================================================================
--- tool_via.c	(revision 34426)
+++ tool_via.c	(revision 34427)
@@ -48,9 +48,6 @@
 
 #include "obj_pstk_draw.h"
 
-TODO("pstk #21: remove this when via is removed and the padstack is created from style directly")
-#include "src_plugins/lib_compat_help/pstk_compat.h"
-
 #include "brave.h"
 
 void pcb_tool_via_notify_mode(rnd_hidlib_t *hl)
@@ -63,24 +60,9 @@
 		return;
 	}
 
+	ps = pcb_pstk_new(pcb->Data, -1, conf_core.design.via_proto,
+		hl->tool_x, hl->tool_y, conf_core.design.clearance, pcb_flag_make(PCB_FLAG_CLEARLINE));
 
-
-	if (pcb_brave & PCB_BRAVE_LIHATA_V8) {
-		ps = pcb_pstk_new(pcb->Data, -1, conf_core.design.via_proto,
-			hl->tool_x, hl->tool_y, conf_core.design.clearance, pcb_flag_make(PCB_FLAG_CLEARLINE));
-	}
-	else {
-TODO("pstk #21: remove this branch in favor of pstk protos - scconfig also has TODO #21, fix it there too")
-		if (conf_core.design.via_drilling_hole >= conf_core.design.via_thickness) {
-			rnd_message(RND_MSG_ERROR, "Can't place via: invalid via geometry (hole too large for via size)\n");
-			return;
-		}
-
-		ps = pcb_pstk_new_compat_via(pcb->Data, -1, hl->tool_x, hl->tool_y,
-			conf_core.design.via_drilling_hole, conf_core.design.via_thickness, conf_core.design.clearance,
-			0, PCB_PSTK_COMPAT_ROUND, rnd_true);
-	}
-
 	if (ps == NULL)
 		return;
 
@@ -95,17 +77,9 @@
 	pcb_draw();
 }
 
-TODO("pstk #21: remove this")
-static void xor_draw_fake_via(rnd_coord_t x, rnd_coord_t y, rnd_coord_t dia, rnd_coord_t clearance)
-{
-	rnd_coord_t r = (dia/2)+clearance;
-	rnd_render->draw_arc(pcb_crosshair.GC, x, y, r, r, 0, 360);
-}
 
-
 void pcb_tool_via_draw_attached(rnd_hidlib_t *hl)
 {
-	if (pcb_brave & PCB_BRAVE_LIHATA_V8) {
 		static pcb_pstk_t ps; /* initialized to all-zero */
 
 		ps.parent.data = PCB->Data;
@@ -126,17 +100,6 @@
 			pcb_pstk_thindraw(&info, pcb_crosshair.GC, &ps);
 			rnd_render->set_color(pcb_crosshair.GC, &conf_core.appearance.color.attached);
 		}
-	}
-	else {
-TODO("pstk #21: remove this branch")
-		xor_draw_fake_via(pcb_crosshair.X, pcb_crosshair.Y, conf_core.design.via_thickness, 0);
-		if (conf_core.editor.show_drc) {
-			/* XXX: Naughty cheat - use the mask to draw DRC clearance! */
-			rnd_render->set_color(pcb_crosshair.GC, &conf_core.appearance.color.drc);
-			xor_draw_fake_via(pcb_crosshair.X, pcb_crosshair.Y, conf_core.design.via_thickness, conf_core.design.clearance);
-			rnd_render->set_color(pcb_crosshair.GC, &conf_core.appearance.color.attached);
-		}
-	}
 }
 
 /* XPM */