Index: trunk/src_plugins/lib_hid_pcbui/lib_hid_pcbui.c
===================================================================
--- trunk/src_plugins/lib_hid_pcbui/lib_hid_pcbui.c	(revision 34427)
+++ trunk/src_plugins/lib_hid_pcbui/lib_hid_pcbui.c	(revision 34428)
@@ -114,8 +114,7 @@
 
 int pplg_init_lib_hid_pcbui(void)
 {
-TODO("pstk #21: remove some paths when route style has proto")
-	const char *rpaths[] = {"design/line_thickness", "design/via_thickness", "design/via_drilling_hole", "design/clearance", NULL};
+	const char *rpaths[] = {"design/line_thickness", "design/clearance", NULL};
 	const char *stpaths[] = { "editor/show_solder_side", "design/line_thickness", "editor/all_direction_lines", "editor/line_refraction", "editor/rubber_band_mode", "design/via_thickness", "design/via_drilling_hole", "design/clearance", "design/text_scale", "design/text_thickness", "editor/buffer_number", "editor/grid_unit", "editor/grid", "appearance/compact", NULL };
 	const char *rdpaths[] = { "editor/grid_unit", "appearance/compact", NULL };
 	const char *ibpaths[] = { "rc/file_changed_interval", NULL };
Index: trunk/src_plugins/lib_hid_pcbui/routest_dlg.c
===================================================================
--- trunk/src_plugins/lib_hid_pcbui/routest_dlg.c	(revision 34427)
+++ trunk/src_plugins/lib_hid_pcbui/routest_dlg.c	(revision 34428)
@@ -35,7 +35,7 @@
 	RND_DAD_DECL_NOINIT(dlg)
 	int active; /* already open - allow only one instance */
 	int curr;
-	int wname, wlineth, wclr, wtxtscale, wtxtth, wfont, wproto, wviahole, wviaring, wattr;
+	int wname, wlineth, wclr, wtxtscale, wtxtth, wfont, wproto, wattr;
 
 	rnd_hidval_t name_timer;
 
@@ -97,23 +97,14 @@
 	hv.crd = rst->Clearance;
 	rnd_gui->attr_dlg_set_value(rstdlg_ctx.dlg_hid_ctx, rstdlg_ctx.wclr, &hv);
 
-	if (pcb_brave & PCB_BRAVE_LIHATA_V8) {
-		if (rst->via_proto_set) {
-			sprintf(tmp, "#%ld", (long int)rst->via_proto);
-			hv.str = tmp;
-		}
-		else
-			hv.str = "<unset>";
-		rnd_gui->attr_dlg_set_value(rstdlg_ctx.dlg_hid_ctx, rstdlg_ctx.wproto, &hv);
+	if (rst->via_proto_set) {
+		sprintf(tmp, "#%ld", (long int)rst->via_proto);
+		hv.str = tmp;
 	}
-	else {
-		hv.crd = rst->Hole;
-		rnd_gui->attr_dlg_set_value(rstdlg_ctx.dlg_hid_ctx, rstdlg_ctx.wviahole, &hv);
+	else
+		hv.str = "<unset>";
+	rnd_gui->attr_dlg_set_value(rstdlg_ctx.dlg_hid_ctx, rstdlg_ctx.wproto, &hv);
 
-		hv.crd = rst->Diameter;
-		rnd_gui->attr_dlg_set_value(rstdlg_ctx.dlg_hid_ctx, rstdlg_ctx.wviaring, &hv);
-	}
-
 	rnd_dad_tree_clear(tree);
 
 	for(a = rst->attr.List, n = 0; n < rst->attr.Number; a++,n++) {
@@ -211,24 +202,6 @@
 	}
 	else if (idx == rstdlg_ctx.wclr)
 		pcb_route_style_change(PCB, rstdlg_ctx.curr, NULL, NULL, NULL, NULL, &attr->val.crd, NULL, 1);
-	else if (idx == rstdlg_ctx.wviahole) {
-		rst->Hole = attr->val.crd;
-		if (rst->Hole * 1.1 >= rstdlg_ctx.dlg[rstdlg_ctx.wviaring].val.crd) {
-			hv.crd = rst->Hole * 1.1;
-			rnd_gui->attr_dlg_set_value(rstdlg_ctx.dlg_hid_ctx, rstdlg_ctx.wviaring, &hv);
-			rst->Diameter = hv.crd;
-		}
-		rst_updated(rst);
-	}
-	else if (idx == rstdlg_ctx.wviaring) {
-		rst->Diameter = attr->val.crd;
-		if (rst->Diameter / 1.1 <= rstdlg_ctx.dlg[rstdlg_ctx.wviahole].val.crd) {
-			hv.crd = rst->Diameter / 1.1;
-			rnd_gui->attr_dlg_set_value(rstdlg_ctx.dlg_hid_ctx, rstdlg_ctx.wviahole, &hv);
-			rst->Hole = hv.crd;
-		}
-		rst_updated(rst);
-	}
 	else if (idx == rstdlg_ctx.wproto) {
 		fgw_error_t err;
 		fgw_arg_t res, args[4];
@@ -333,17 +306,6 @@
 
 	idx_changed(); /* flush pending timed changes */
 
-	if (!(pcb_brave & PCB_BRAVE_LIHATA_V8)) {
-		pcb_route_style_t *rst = vtroutestyle_get(&PCB->RouteStyle, ctx->curr, 0);
-
-		TODO("pstk #21: remove this branch");
-
-		if (rst->Diameter <= rst->Hole) {
-			rnd_message(RND_MSG_ERROR, "had to increase the via ring diameter - can not be smaller than the hole");
-			rst->Diameter = rst->Hole+RND_MIL_TO_COORD(1);
-		}
-	}
-
 	RND_DAD_FREE(ctx->dlg);
 	memset(ctx, 0, sizeof(rstdlg_ctx_t)); /* reset all states to the initial - includes ctx->active = 0; */
 }
@@ -403,29 +365,14 @@
 				RND_DAD_HELP(rstdlg_ctx.dlg, "Text font ID (button invokes the font selector)");
 				RND_DAD_CHANGE_CB(rstdlg_ctx.dlg, rst_change_cb);
 
-			if (pcb_brave & PCB_BRAVE_LIHATA_V8) {
-				RND_DAD_LABEL(rstdlg_ctx.dlg, "Via padstack:");
-				RND_DAD_BUTTON(rstdlg_ctx.dlg, "<pid>");
-					rstdlg_ctx.wproto = RND_DAD_CURRENT(rstdlg_ctx.dlg);
-					RND_DAD_HELP(rstdlg_ctx.dlg, "Padstack prototype ID used for new vias with this style\n(button invokes the board padstack proto list dialog)");
-					RND_DAD_CHANGE_CB(rstdlg_ctx.dlg, rst_change_cb);
-			}
-			else {
-				RND_DAD_LABEL(rstdlg_ctx.dlg, "*Via hole:");
-				RND_DAD_COORD(rstdlg_ctx.dlg);
-					rstdlg_ctx.wviahole = RND_DAD_CURRENT(rstdlg_ctx.dlg);
-					RND_DAD_HELP(rstdlg_ctx.dlg, "Via hole diameter\nwarning: will be replaced with the padstack selector");
-					RND_DAD_MINMAX(rstdlg_ctx.dlg, 1, RND_MAX_COORD);
-					RND_DAD_CHANGE_CB(rstdlg_ctx.dlg, rst_change_cb);
 
-				RND_DAD_LABEL(rstdlg_ctx.dlg, "*Via ring:");
-				RND_DAD_COORD(rstdlg_ctx.dlg);
-					rstdlg_ctx.wviaring = RND_DAD_CURRENT(rstdlg_ctx.dlg);
-					RND_DAD_HELP(rstdlg_ctx.dlg, "Via ring diameter\nwarning: will be replaced with the padstack selector");
-					RND_DAD_MINMAX(rstdlg_ctx.dlg, 1, RND_MAX_COORD);
-					RND_DAD_CHANGE_CB(rstdlg_ctx.dlg, rst_change_cb);
-			}
+			RND_DAD_LABEL(rstdlg_ctx.dlg, "Via padstack:");
+			RND_DAD_BUTTON(rstdlg_ctx.dlg, "<pid>");
+				rstdlg_ctx.wproto = RND_DAD_CURRENT(rstdlg_ctx.dlg);
+				RND_DAD_HELP(rstdlg_ctx.dlg, "Padstack prototype ID used for new vias with this style\n(button invokes the board padstack proto list dialog)");
+				RND_DAD_CHANGE_CB(rstdlg_ctx.dlg, rst_change_cb);
 
+
 		RND_DAD_END(rstdlg_ctx.dlg);
 		RND_DAD_TREE(rstdlg_ctx.dlg, 2, 0, attr_hdr);
 			RND_DAD_HELP(rstdlg_ctx.dlg, "These attributes are automatically added to\nany object drawn with this routing style");