Index: trunk/doc/TODO
===================================================================
--- trunk/doc/TODO	(revision 36979)
+++ trunk/doc/TODO	(revision 36980)
@@ -57,6 +57,8 @@
 	- keep numeric format: test all
 	- keep unknown subtrees
 	- BUG: lhtpers indentation: bug_files/lhtpers_ins/; breakpoint in pers_table.c:34 and debug why the newline is getting in [report: Igor2]
+- FEATURE: lihata board v9:
+	- replace board/size with the bbox representation
 - BUG: I/O bugs:
 	- eagle:
 		- BUG: xml: eagle XML import fails on polygon import reported by miloh, test file pcb-rnd-aux poly_selfi/eagle_polygon_crash.brd [report: erich], due to input file containing an invalid polygon: a self intersecting poly in line 156 - consider handling "width"?
Index: trunk/src/board.c
===================================================================
--- trunk/src/board.c	(revision 36979)
+++ trunk/src/board.c	(revision 36980)
@@ -97,7 +97,8 @@
 	/* NOTE: we used to set all the pcb flags on ptr here, but we don't need to do that anymore due to the new conf system */
 	ptr->hidlib.grid = rnd_conf.editor.grid;
 
-	ptr->hidlib.size_y = ptr->hidlib.size_x = RND_MM_TO_COORD(20); /* should be overriden by the default design */
+	ptr->hidlib.dwg.Y1 = ptr->hidlib.dwg.X1 = 0;
+	ptr->hidlib.dwg.Y2 = ptr->hidlib.dwg.X2 = RND_MM_TO_COORD(20); /* should be overriden by the default design */
 	ptr->ID = pcb_create_ID_get();
 	ptr->ThermScale = 0.5;
 
@@ -266,10 +267,12 @@
 	return rnd_true;
 }
 
-static void pcb_board_resize_(pcb_board_t *pcb, rnd_coord_t Width, rnd_coord_t Height)
+static void pcb_board_resize_(pcb_board_t *pcb, rnd_coord_t x1, rnd_coord_t y1, rnd_coord_t x2, rnd_coord_t y2)
 {
-	pcb->hidlib.size_x = Width;
-	pcb->hidlib.size_y = Height;
+	pcb->hidlib.dwg.X1 = x1;
+	pcb->hidlib.dwg.Y1 = y1;
+	pcb->hidlib.dwg.X2 = x2;
+	pcb->hidlib.dwg.Y2 = y2;
 
 	if (pcb == PCB)
 		pcb_board_replaced(0);
@@ -279,7 +282,7 @@
 
 typedef struct {
 	pcb_board_t *pcb;
-	rnd_coord_t w, h;
+	rnd_coord_t x1, y1, x2, y2;
 	double thermal_scale;
 } undo_board_size_t;
 
@@ -287,11 +290,12 @@
 {
 	undo_board_size_t *s = udata;
 
-	if ((s->w != s->pcb->hidlib.size_x) || (s->h != s->pcb->hidlib.size_y)) {
-		rnd_coord_t oldw = s->pcb->hidlib.size_x, oldh = s->pcb->hidlib.size_y;
-		pcb_board_resize_(s->pcb, s->w, s->h);
-		s->w = oldw;
-		s->h = oldh;
+	if ((s->x1 != s->pcb->hidlib.dwg.X1) || (s->y1 != s->pcb->hidlib.dwg.Y1) || (s->x2 != s->pcb->hidlib.dwg.X2) || (s->y2 != s->pcb->hidlib.dwg.Y2)) {
+		rnd_coord_t old_x1 = s->pcb->hidlib.dwg.X1, old_y1 = s->pcb->hidlib.dwg.Y1;
+		rnd_coord_t old_x2 = s->pcb->hidlib.dwg.X2, old_y2 = s->pcb->hidlib.dwg.Y2;
+		pcb_board_resize_(s->pcb, s->x1, s->y1, s->x2, s->y2);
+		s->x1 = old_x1; s->y1 = old_y1;
+		s->x2 = old_x2; s->y2 = old_y2;
 	}
 	if (s->thermal_scale != s->pcb->ThermScale) {
 		rnd_swap(double, s->thermal_scale, s->pcb->ThermScale);
@@ -304,8 +308,8 @@
 static void undo_board_size_print(void *udata, char *dst, size_t dst_len)
 {
 	undo_board_size_t *s = udata;
-	if ((s->w != s->pcb->hidlib.size_x) || (s->w != s->pcb->hidlib.size_y))
-		rnd_snprintf(dst, dst_len, "board_size: %mmx%mm ", s->w, s->h);
+	if ((s->x1 != s->pcb->hidlib.dwg.X1) || (s->y1 != s->pcb->hidlib.dwg.Y1) || (s->x2 != s->pcb->hidlib.dwg.X2) || (s->y2 != s->pcb->hidlib.dwg.Y2))
+		rnd_snprintf(dst, dst_len, "board_size: %mm;%mm .. %mm;%mm ", s->x1, s->y1, s->x2, s->y2);
 	if (s->thermal_scale != s->pcb->ThermScale)
 		rnd_snprintf(dst, dst_len, "thermal scale: %f", s->thermal_scale);
 }
@@ -318,19 +322,24 @@
 	undo_board_size_print
 };
 
-void pcb_board_resize(rnd_coord_t width, rnd_coord_t height, int undoable)
+void pcb_board_resize(rnd_coord_t x1, rnd_coord_t y1, rnd_coord_t x2, rnd_coord_t y2, int undoable)
 {
 	undo_board_size_t *s;
 
 	if (!undoable) {
-		pcb_board_resize_(PCB, width, height);
+		pcb_board_resize_(PCB, x1, y1, x2, y2);
 		return;
 	}
 
+	if ((x1 != 0) || (y1 != 0))
+		rnd_message(RND_MSG_ERROR, "pcb_board_resize(): drawing area should start at 0;0 for compatibility reasons\n");
+
 	s = pcb_undo_alloc(PCB, &undo_board_size, sizeof(undo_board_size_t));
 	s->pcb = PCB;
-	s->w = width;
-	s->h = height;
+	s->x1 = x1;
+	s->y1 = y1;
+	s->x2 = x2;
+	s->y2 = y2;
 	s->thermal_scale = PCB->ThermScale;
 	undo_board_size_swap(s);
 }
@@ -348,8 +357,10 @@
 
 	s = pcb_undo_alloc(PCB, &undo_board_size, sizeof(undo_board_size_t));
 	s->pcb = PCB;
-	s->w = PCB->hidlib.size_x;
-	s->h = PCB->hidlib.size_y;
+	s->x1 = PCB->hidlib.dwg.X1;
+	s->y1 = PCB->hidlib.dwg.Y1;
+	s->x2 = PCB->hidlib.dwg.X2;
+	s->y2 = PCB->hidlib.dwg.Y2;
 	s->thermal_scale = thermal_scale;
 	undo_board_size_swap(s);
 }
@@ -392,13 +403,13 @@
 	if (pcb_data_bbox(&b, pcb->Data, rnd_false) == NULL)
 		return -1;
 
-	if ((b.X2 - b.X1) > pcb->hidlib.size_x) {
-		pcb->hidlib.size_x = b.X2 - b.X1;
+	if ((b.X2 - b.X1) > pcb->hidlib.dwg.X2) {
+		pcb->hidlib.dwg.X2 = b.X2 - b.X1;
 		chg++;
 	}
 
-	if ((b.Y2 - b.Y1) > pcb->hidlib.size_y) {
-		pcb->hidlib.size_y = b.Y2 - b.Y1;
+	if ((b.Y2 - b.Y1) > pcb->hidlib.dwg.Y2) {
+		pcb->hidlib.dwg.Y2 = b.Y2 - b.Y1;
 		chg++;
 	}
 
Index: trunk/src/board.h
===================================================================
--- trunk/src/board.h	(revision 36979)
+++ trunk/src/board.h	(revision 36980)
@@ -132,7 +132,7 @@
 void pcb_board_count_slots(pcb_board_t *pcb, int *plated, int *unplated, const rnd_box_t *within_area);
 
 #define	PCB_SWAP_X(x)		(RND_SWAP_SIGN_X(x))
-#define	PCB_SWAP_Y(y)		(PCB->hidlib.size_y +RND_SWAP_SIGN_Y(y))
+#define	PCB_SWAP_Y(y)		(PCB->hidlib.dwg.Y2 +RND_SWAP_SIGN_Y(y))
 
 #define	PCB_CSWAP_X(x, w, cond)		((cond) ? (RND_SWAP_SIGN_X(x)) : (x))
 #define	PCB_CSWAP_Y(y, h, cond)		((cond) ? (h+RND_SWAP_SIGN_Y(y)) : (y))
@@ -146,7 +146,7 @@
 
 /* changes the maximum size of a layout, notifies the GUI
  * and adjusts the cursor confinement box */
-void pcb_board_resize(rnd_coord_t Width, rnd_coord_t Height, int undoable);
+void pcb_board_resize(rnd_coord_t x1, rnd_coord_t y1, rnd_coord_t x2, rnd_coord_t y2, int undoable);
 
 /* change the thermal scale of the board, update the GUI */
 void pcb_board_chg_thermal_scale(double thermal_scale, int undoable);
Index: trunk/src/buffer.c
===================================================================
--- trunk/src/buffer.c	(revision 36979)
+++ trunk/src/buffer.c	(revision 36980)
@@ -718,7 +718,7 @@
 /* this results in saving flipped (bottom-side) footprints whenlooking at the board from the bottom */
 	PCB_SUBC_LOOP(Buffer->Data);
 	{
-		pcb_subc_change_side(subc, /*2 * pcb_crosshair.Y - pcb->hidlib.size_y*/0);
+		pcb_subc_change_side(subc, /*2 * pcb_crosshair.Y - pcb->hidlib.dwg.Y2*/0);
 	}
 	PCB_END_LOOP;
 #endif
Index: trunk/src/crosshair.c
===================================================================
--- trunk/src/crosshair.c	(revision 36979)
+++ trunk/src/crosshair.c	(revision 36980)
@@ -915,8 +915,8 @@
 
 	oldx = pcb_crosshair.X;
 	oldy = pcb_crosshair.Y;
-	pcb->hidlib.ch_x = pcb_crosshair.X = RND_CLAMP(X, -pcb->hidlib.size_x/2, pcb->hidlib.size_x*3/2);
-	pcb->hidlib.ch_y = pcb_crosshair.Y = RND_CLAMP(Y, -pcb->hidlib.size_y/2, pcb->hidlib.size_y*3/2);
+	pcb->hidlib.ch_x = pcb_crosshair.X = RND_CLAMP(X, pcb->hidlib.dwg.X1 - rnd_dwg_get_size_x(&pcb->hidlib)/2, pcb->hidlib.dwg.X2 + rnd_dwg_get_size_x(&pcb->hidlib)/2);
+	pcb->hidlib.ch_y = pcb_crosshair.Y = RND_CLAMP(Y, pcb->hidlib.dwg.Y1 - rnd_dwg_get_size_y(&pcb->hidlib)/2, pcb->hidlib.dwg.Y2 + rnd_dwg_get_size_y(&pcb->hidlib)/2);
 
 	nearest_grid_x = rnd_grid_fit(pcb_crosshair.X, pcb->hidlib.grid, pcb->hidlib.grid_ox);
 	nearest_grid_y = rnd_grid_fit(pcb_crosshair.Y, pcb->hidlib.grid, pcb->hidlib.grid_oy);
Index: trunk/src/draw_composite.c
===================================================================
--- trunk/src/draw_composite.c	(revision 36979)
+++ trunk/src/draw_composite.c	(revision 36980)
@@ -43,7 +43,7 @@
 {
 	rnd_render->set_color(pcb_draw_out.fgGC, ctx->color);
 	if (ctx->info->drawn_area == NULL)
-		rnd_render->fill_rect(pcb_draw_out.fgGC, 0, 0, ctx->info->pcb->hidlib.size_x, ctx->info->pcb->hidlib.size_y);
+		rnd_render->fill_rect(pcb_draw_out.fgGC, ctx->info->pcb->hidlib.dwg.X1, ctx->info->pcb->hidlib.dwg.Y1, ctx->info->pcb->hidlib.dwg.X2, ctx->info->pcb->hidlib.dwg.Y2);
 	else
 		rnd_render->fill_rect(pcb_draw_out.fgGC, ctx->info->drawn_area->X1, ctx->info->drawn_area->Y1, ctx->info->drawn_area->X2, ctx->info->drawn_area->Y2);
 }
Index: trunk/src/draw_ly_spec.c
===================================================================
--- trunk/src/draw_ly_spec.c	(revision 36979)
+++ trunk/src/draw_ly_spec.c	(revision 36980)
@@ -293,7 +293,7 @@
 		rnd_render->set_color(pcb_draw_out.fgGC, &PCB->Data->Layer[goutl->lid[0]].meta.real.color);
 		rnd_hid_set_line_cap(pcb_draw_out.fgGC, rnd_cap_round);
 		rnd_hid_set_line_width(pcb_draw_out.fgGC, conf_core.design.min_wid);
-		rnd_render->draw_rect(pcb_draw_out.fgGC, 0, 0, PCB->hidlib.size_x, PCB->hidlib.size_y);
+		rnd_render->draw_rect(pcb_draw_out.fgGC, PCB->hidlib.dwg.X1, PCB->hidlib.dwg.Y1, PCB->hidlib.dwg.X2, PCB->hidlib.dwg.Y2);
 
 		rnd_render->set_drawing_mode(rnd_render, RND_HID_COMP_FLUSH, pcb_draw_out.direct, info->drawn_area);
 		rnd_render->end_layer(rnd_render);
Index: trunk/src/file_act.c
===================================================================
--- trunk/src/file_act.c	(revision 36979)
+++ trunk/src/file_act.c	(revision 36980)
@@ -181,7 +181,7 @@
 		pcb->hidlib.name = name;
 
 		pcb_layervis_reset_stack(&pcb->hidlib);
-		pcb_center_display(pcb, pcb->hidlib.size_x / 2, pcb->hidlib.size_y / 2);
+		pcb_center_display(pcb, (pcb->hidlib.dwg.X1+pcb->hidlib.dwg.X2) / 2, (pcb->hidlib.dwg.Y1+pcb->hidlib.dwg.Y2) / 2);
 		pcb_board_replaced(0);
 		rnd_hid_redraw(pcb);
 		rnd_hid_notify_crosshair_change(RND_ACT_HIDLIB, rnd_true);
Index: trunk/src/obj_subc.c
===================================================================
--- trunk/src/obj_subc.c	(revision 36979)
+++ trunk/src/obj_subc.c	(revision 36980)
@@ -1306,7 +1306,7 @@
 		last = pcb_undo_serial();
 
 		pcb_subc_get_origin(sc, &w, &h);
-		pcb_subc_change_side(sc, 2 * h - PCB->hidlib.size_y);
+		pcb_subc_change_side(sc, 2 * h - PCB->hidlib.dwg.Y2);
 		pcb_undo_truncate_from(last);
 		
 	}
@@ -1395,7 +1395,7 @@
 		PCB_SUBC_LOOP(PCB->Data);
 		{
 			if (PCB_FLAG_TEST(PCB_FLAG_SELECTED, subc)) {
-				change |= pcb_subc_change_side(subc, 2 * pcb_crosshair.Y - PCB->hidlib.size_y);
+				change |= pcb_subc_change_side(subc, 2 * pcb_crosshair.Y - PCB->hidlib.dwg.Y2);
 			}
 		}
 		PCB_END_LOOP;
@@ -2774,7 +2774,7 @@
 	}
 
 	if (dst_on_bottom != src_on_bottom)
-		pcb_subc_change_side(placed, 2 * oy - PCB->hidlib.size_y);
+		pcb_subc_change_side(placed, 2 * oy - PCB->hidlib.dwg.Y2);
 
 	if (pcb_subcrepl_apply_thermals_floaters(&repl, placed)) {
 		pcb_opctx_t clip;
Index: trunk/src/object_act.c
===================================================================
--- trunk/src/object_act.c	(revision 36979)
+++ trunk/src/object_act.c	(revision 36980)
@@ -88,7 +88,7 @@
 	*dx += pcb->hidlib.grid;
 
 	/* Figure out if this row has room.  If not, start a new row */
-	if (GAP + obj->BoundingBox.X2 + *dx > pcb->hidlib.size_x) {
+	if (GAP + obj->BoundingBox.X2 + *dx > pcb->hidlib.dwg.X2) {
 		*miny = *maxy + GAP;
 		*minx = GAP;
 	}
@@ -111,7 +111,7 @@
 	*minx = newx2 + GAP;
 	if (*maxy < newy2) {
 		*maxy = newy2;
-		if (*maxy > pcb->hidlib.size_y - GAP) {
+		if (*maxy > pcb->hidlib.dwg.Y2 - GAP) {
 			*maxy = GAP;
 			rnd_message(RND_MSG_WARNING, "The board is too small for hosting all subcircuits,\ndiesperse restarted from the top.\nExpect overlapping subcircuits\n");
 		}
@@ -179,7 +179,7 @@
 			if ((pcb_search_screen(pcb_crosshair.X, pcb_crosshair.Y, PCB_OBJ_SUBC, &ptrtmp, &ptrtmp, &ptrtmp)) != PCB_OBJ_VOID) {
 				pcb_subc_t *subc = (pcb_subc_t *)ptrtmp;
 				pcb_undo_freeze_serial();
-				pcb_subc_change_side(subc, 2 * pcb_crosshair.Y - RND_ACT_HIDLIB->size_y);
+				pcb_subc_change_side(subc, 2 * pcb_crosshair.Y - RND_ACT_HIDLIB->dwg.Y2);
 				pcb_undo_unfreeze_serial();
 				pcb_undo_inc_serial();
 				pcb_draw();
@@ -378,9 +378,9 @@
 	plc->plc_method = PLC_DISPERSE;
 	plc->rem_method = PLC_SELECT;
 	plc->location = PLC_AT;
-	plc->lx = pcb->hidlib.size_x / 2;
-	plc->ly = pcb->hidlib.size_y / 2;
-	plc->dd = MIN(pcb->hidlib.size_x, pcb->hidlib.size_y) / 10;
+	plc->lx = pcb->hidlib.dwg.X2 / 2;
+	plc->ly = pcb->hidlib.dwg.Y2 / 2;
+	plc->dd = MIN(pcb->hidlib.dwg.X2, pcb->hidlib.dwg.Y2) / 10;
 	plc->c = plc->cx = plc->cy = 0;
 	plc->remlst = NULL;
 
@@ -426,8 +426,8 @@
 				break;
 			}
 		case PLC_CENTER:
-			plc->lx = pcb->hidlib.size_x / 2;
-			plc->ly = pcb->hidlib.size_y / 2;
+			plc->lx = (pcb->hidlib.dwg.X1 + pcb->hidlib.dwg.X2) / 2;
+			plc->ly = (pcb->hidlib.dwg.Y1 + pcb->hidlib.dwg.Y2) / 2;
 			break;
 	}
 
@@ -455,7 +455,7 @@
 			{
 				rnd_coord_t bx = bbx.X2 - bbx.X1, by = bbx.Y2 - bbx.Y1;
 				rnd_coord_t xo = PCB_PASTEBUFFER->X/2, yo = PCB_PASTEBUFFER->Y/2;
-				rnd_coord_t max = (plc->side % 2) ? plc->pcb->hidlib.size_y : plc->pcb->hidlib.size_x;
+				rnd_coord_t max = (plc->side % 2) ? plc->pcb->hidlib.dwg.Y2 : plc->pcb->hidlib.dwg.X2;
 				rnd_coord_t mdim = (plc->side % 2) ? by : bx;
 /*				rnd_coord_t adim = (plc->side % 2) ? bx : by;*/
 				pcb_subc_t *sc;
@@ -469,9 +469,9 @@
 
 				switch(plc->side) {
 					case 0: px = xo2 - bbx.X1 + plc->c; py = yo2 - bbx.Y2; break; /* top */
-					case 1: py = yo2 - bbx.Y1 + plc->c; px = xo2 - bbx.X1 + plc->pcb->hidlib.size_x; break; /* right */
-					case 2: px = plc->pcb->hidlib.size_x - (bbx.X2 - xo2 + plc->c); py = yo2 - bbx.Y1 + plc->pcb->hidlib.size_y; break; /* bottom, from right to left */
-					case 3: py = plc->pcb->hidlib.size_y - (bbx.Y2 - yo2 + plc->c); px = xo2 - bbx.X2; break; /* left, from bottom to top */
+					case 1: py = yo2 - bbx.Y1 + plc->c; px = xo2 - bbx.X1 + plc->pcb->hidlib.dwg.X2; break; /* right */
+					case 2: px = plc->pcb->hidlib.dwg.X2 - (bbx.X2 - xo2 + plc->c); py = yo2 - bbx.Y1 + plc->pcb->hidlib.dwg.Y2; break; /* bottom, from right to left */
+					case 3: py = plc->pcb->hidlib.dwg.Y2 - (bbx.Y2 - yo2 + plc->c); px = xo2 - bbx.X2; break; /* left, from bottom to top */
 				}
 
 				plc->c += (double)mdim + RND_MM_TO_COORD(1);
@@ -653,7 +653,7 @@
 				rnd_coord_t pcx = 0, pcy = 0;
 				pcb_subc_get_origin(psc, &pcx, &pcy);
 				if (!orig_on_top)
-					pcb_subc_change_side(psc, pcy * 2 - RND_ACT_HIDLIB->size_y);
+					pcb_subc_change_side(psc, pcy * 2 - RND_ACT_HIDLIB->dwg.Y2);
 				if (orig_rot != 0) {
 					double cosa, sina;
 					cosa = cos(orig_rot / RND_RAD_TO_DEG);
Index: trunk/src/plug_io.c
===================================================================
--- trunk/src/plug_io.c	(revision 36979)
+++ trunk/src/plug_io.c	(revision 36980)
@@ -643,11 +643,11 @@
 		pcb_board_new_postproc(PCB, 0);
 		if (how == 0) {
 			/* update cursor location */
-			PCB->hidlib.ch_x = pcb_crosshair.X = PCB->hidlib.size_x/2;
-			PCB->hidlib.ch_y = pcb_crosshair.Y = PCB->hidlib.size_y/2;
+			PCB->hidlib.ch_x = pcb_crosshair.X = (PCB->hidlib.dwg.X1 + PCB->hidlib.dwg.X2) / 2;
+			PCB->hidlib.ch_y = pcb_crosshair.Y = (PCB->hidlib.dwg.Y1 + PCB->hidlib.dwg.Y2) / 2;
 
 			/* update cursor confinement and output area (scrollbars) */
-			pcb_board_resize(PCB->hidlib.size_x, PCB->hidlib.size_y, 0);
+			pcb_board_resize(PCB->hidlib.dwg.X1, PCB->hidlib.dwg.Y1, PCB->hidlib.dwg.X2, PCB->hidlib.dwg.Y2, 0);
 		}
 
 		/* have to be called after pcb_board_resize() so vis update is after a board changed update */
@@ -834,7 +834,7 @@
 				res = -1;
 			}
 			else
-				pcb_board_resize(b.X2*1.5, b.Y2*1.5, 0);
+				pcb_board_resize(b.X1, b.Y1, b.X2*1.5, b.Y2*1.5, 0);
 		}
 	}
 	return res;
Index: trunk/src_plugins/act_read/act_read.c
===================================================================
--- trunk/src_plugins/act_read/act_read.c	(revision 36979)
+++ trunk/src_plugins/act_read/act_read.c	(revision 36980)
@@ -100,11 +100,11 @@
 	switch(cmd) {
 		case act_read_keywords_width:
 		case act_read_keywords_size_x:
-			res->type = FGW_COORD; fgw_coord(res) = pcb->hidlib.size_x;
+			res->type = FGW_COORD; fgw_coord(res) = rnd_dwg_get_size_x(&pcb->hidlib);
 			return 0;
 		case act_read_keywords_height:
 		case act_read_keywords_size_y:
-			res->type = FGW_COORD; fgw_coord(res) = pcb->hidlib.size_y;
+			res->type = FGW_COORD; fgw_coord(res) = rnd_dwg_get_size_y(&pcb->hidlib);
 			return 0;
 		default:
 			return FGW_ERR_ARG_CONV;
Index: trunk/src_plugins/ar_cpcb/ar_cpcb.c
===================================================================
--- trunk/src_plugins/ar_cpcb/ar_cpcb.c	(revision 36979)
+++ trunk/src_plugins/ar_cpcb/ar_cpcb.c	(revision 36980)
@@ -258,7 +258,7 @@
 	rnd_coord_t via_dia2 = pcb_pstk_pen_dia(PCB) / 2;
 
 	/* print dims */
-	rnd_fprintf(f, "(%d %d %d)\n", (int)(RND_COORD_TO_MM(pcb->hidlib.size_x)+0.5), (int)(RND_COORD_TO_MM(pcb->hidlib.size_y)+0.5), stack->maxlayer);
+	rnd_fprintf(f, "(%d %d %d)\n", (int)(RND_COORD_TO_MM(pcb->hidlib.dwg.X2)+0.5), (int)(RND_COORD_TO_MM(pcb->hidlib.dwg.Y2)+0.5), stack->maxlayer);
 
 	/* print tracks */
 	for(e = htpp_first(&nmap->netmap.n2o); e != NULL; e = htpp_next(&nmap->netmap.n2o, e)) {
Index: trunk/src_plugins/autocrop/autocrop.c
===================================================================
--- trunk/src_plugins/autocrop/autocrop.c	(revision 36979)
+++ trunk/src_plugins/autocrop/autocrop.c	(revision 36980)
@@ -54,13 +54,13 @@
 	w = ((box.X2 + dx) / PCB->hidlib.grid + 2) * PCB->hidlib.grid;
 	h = ((box.Y2 + dy) / PCB->hidlib.grid + 2) * PCB->hidlib.grid;
 
-	if ((dx == 0) && (dy == 0) && (w == PCB->hidlib.size_x) && (h == PCB->hidlib.size_y))
+	if ((dx == 0) && (dy == 0) && (w == PCB->hidlib.dwg.X2) && (h == PCB->hidlib.dwg.Y2))
 		return 0;
 
 	pcb_draw_inhibit_inc();
 	pcb_data_clip_inhibit_inc(PCB->Data);
 	pcb_data_move(PCB->Data, dx, dy, 1);
-	pcb_board_resize(w, h, 1);
+	pcb_board_resize(0, 0, w, h, 1);
 	pcb_data_clip_inhibit_dec(PCB->Data, 1);
 	pcb_draw_inhibit_dec();
 
Index: trunk/src_plugins/autoplace/autoplace.c
===================================================================
--- trunk/src_plugins/autoplace/autoplace.c	(revision 36979)
+++ trunk/src_plugins/autoplace/autoplace.c	(revision 36980)
@@ -268,9 +268,10 @@
 	ni.trap = *box;
 	ni.search_dir = search_direction;
 
-	bbox.X1 = bbox.Y1 = 0;
-	bbox.X2 = PCB->hidlib.size_x;
-	bbox.Y2 = PCB->hidlib.size_y;
+	bbox.X1 = PCB->hidlib.dwg.X1;
+	bbox.Y1 = PCB->hidlib.dwg.Y2;
+	bbox.X2 = PCB->hidlib.dwg.X2;
+	bbox.Y2 = PCB->hidlib.dwg.Y2;
 	/* rotate so that we can use the 'north' case for everything */
 	RND_BOX_ROTATE_TO_NORTH(bbox, search_direction);
 	RND_BOX_ROTATE_TO_NORTH(ni.trap, search_direction);
@@ -592,8 +593,8 @@
 	case 0:
 		{														/* shift! */
 			rnd_coord_t grid;
-			double scaleX = RND_CLAMP(sqrt(T), RND_MIL_TO_COORD(2.5), PCB->hidlib.size_x / 3);
-			double scaleY = RND_CLAMP(sqrt(T), RND_MIL_TO_COORD(2.5), PCB->hidlib.size_y / 3);
+			double scaleX = RND_CLAMP(sqrt(T), RND_MIL_TO_COORD(2.5), rnd_dwg_get_size_x(&PCB->hidlib) / 3);
+			double scaleY = RND_CLAMP(sqrt(T), RND_MIL_TO_COORD(2.5), rnd_dwg_get_size_y(&PCB->hidlib) / 3);
 			pt.which = SHIFT;
 			pt.DX = scaleX * 2 * ((((double) rnd_rand()) / RAND_MAX) - 0.5);
 			pt.DY = scaleY * 2 * ((((double) rnd_rand()) / RAND_MAX) - 0.5);
@@ -605,10 +606,10 @@
 			/* limit DX/DY so we don't fall off board */
 			{
 				pcb_subc_t *s = (pcb_subc_t *)pt.comp;
-				pt.DX = MAX(pt.DX, -s->BoundingBox.X1);
-				pt.DX = MIN(pt.DX, PCB->hidlib.size_x - s->BoundingBox.X2);
-				pt.DY = MAX(pt.DY, -s->BoundingBox.Y1);
-				pt.DY = MIN(pt.DY, PCB->hidlib.size_y - s->BoundingBox.Y2);
+				pt.DX = MAX(pt.DX, PCB->hidlib.dwg.X1 - s->BoundingBox.X1);
+				pt.DX = MIN(pt.DX, PCB->hidlib.dwg.X2 - s->BoundingBox.X2);
+				pt.DY = MAX(pt.DY, PCB->hidlib.dwg.Y1 - s->BoundingBox.Y1);
+				pt.DY = MIN(pt.DY, PCB->hidlib.dwg.Y2 - s->BoundingBox.Y2);
 			}
 			/* all done but the movin' */
 			break;
Index: trunk/src_plugins/autoroute/autoroute.c
===================================================================
--- trunk/src_plugins/autoroute/autoroute.c	(revision 36979)
+++ trunk/src_plugins/autoroute/autoroute.c	(revision 36980)
@@ -1163,9 +1163,10 @@
 	rd->max_bloat = BLOAT(&rd->defaultstyle);
 	rd->max_keep = conf_core.design.clearance;
 	/* create styles structures */
-	bbox.X1 = bbox.Y1 = 0;
-	bbox.X2 = PCB->hidlib.size_x;
-	bbox.Y2 = PCB->hidlib.size_y;
+	bbox.X1 = PCB->hidlib.dwg.X1;
+	bbox.Y1 = PCB->hidlib.dwg.Y1;
+	bbox.X2 = PCB->hidlib.dwg.X2;
+	bbox.Y2 = PCB->hidlib.dwg.Y2;
 	for (i = 0; i < rd->max_styles + 1; i++) {
 		pcb_route_style_t *style = (i < rd->max_styles) ? &PCB->RouteStyle.array[i] : &rd->defaultstyle;
 		rd->styles[i] = style;
@@ -2080,10 +2081,10 @@
 	 */
 	switch (e->expand_dir) {
 	case RND_ANY_DIR:
-		ans.inflated.X1 = (e->rb->came_from == RND_EAST ? ans.orig.X1 : 0);
-		ans.inflated.Y1 = (e->rb->came_from == RND_SOUTH ? ans.orig.Y1 : 0);
-		ans.inflated.X2 = (e->rb->came_from == RND_WEST ? ans.orig.X2 : PCB->hidlib.size_x);
-		ans.inflated.Y2 = (e->rb->came_from == RND_NORTH ? ans.orig.Y2 : PCB->hidlib.size_y);
+		ans.inflated.X1 = (e->rb->came_from == RND_EAST ? ans.orig.X1 : PCB->hidlib.dwg.X1);
+		ans.inflated.Y1 = (e->rb->came_from == RND_SOUTH ? ans.orig.Y1 : PCB->hidlib.dwg.Y1);
+		ans.inflated.X2 = (e->rb->came_from == RND_WEST ? ans.orig.X2 : PCB->hidlib.dwg.X2);
+		ans.inflated.Y2 = (e->rb->came_from == RND_NORTH ? ans.orig.Y2 : PCB->hidlib.dwg.Y2);
 		if (e->rb->came_from == RND_NORTH)
 			ans.done = noshrink = _SOUTH;
 		else if (e->rb->came_from == RND_EAST)
@@ -2107,7 +2108,7 @@
 		ans.done = _SOUTH + _WEST;
 		noshrink = 0;
 		ans.inflated.X1 = box->X1 - ans.bloat;
-		ans.inflated.X2 = PCB->hidlib.size_x;
+		ans.inflated.X2 = PCB->hidlib.dwg.X2;
 		ans.inflated.Y2 = box->Y2 + ans.bloat;
 		ans.inflated.Y1 = 0;
 		break;
@@ -2117,14 +2118,14 @@
 		ans.inflated.Y1 = box->Y1 - ans.bloat;
 		ans.inflated.Y2 = box->Y2 + ans.bloat;
 		ans.inflated.X1 = box->X1;
-		ans.inflated.X2 = PCB->hidlib.size_x;
+		ans.inflated.X2 = PCB->hidlib.dwg.X2;
 		break;
 	case RND_SE:
 		ans.done = _NORTH + _WEST;
 		noshrink = 0;
 		ans.inflated.X1 = box->X1 - ans.bloat;
-		ans.inflated.X2 = PCB->hidlib.size_x;
-		ans.inflated.Y2 = PCB->hidlib.size_y;
+		ans.inflated.X2 = PCB->hidlib.dwg.X2;
+		ans.inflated.Y2 = PCB->hidlib.dwg.Y2;
 		ans.inflated.Y1 = box->Y1 - ans.bloat;
 		break;
 	case RND_SOUTH:
@@ -2133,7 +2134,7 @@
 		ans.inflated.X1 = box->X1 - ans.bloat;
 		ans.inflated.X2 = box->X2 + ans.bloat;
 		ans.inflated.Y1 = box->Y1;
-		ans.inflated.Y2 = PCB->hidlib.size_y;
+		ans.inflated.Y2 = PCB->hidlib.dwg.Y2;
 		break;
 	case RND_SW:
 		ans.done = _NORTH + _EAST;
@@ -2140,7 +2141,7 @@
 		noshrink = 0;
 		ans.inflated.X1 = 0;
 		ans.inflated.X2 = box->X2 + ans.bloat;
-		ans.inflated.Y2 = PCB->hidlib.size_y;
+		ans.inflated.Y2 = PCB->hidlib.dwg.Y2;
 		ans.inflated.Y1 = box->Y1 - ans.bloat;
 		break;
 	case RND_WEST:
@@ -2175,11 +2176,11 @@
 	else
 		ans.done |= _NORTH;
 	if (ans.e && !boink_box(ans.e, &ans, RND_EAST))
-		ans.inflated.X2 = PCB->hidlib.size_x;
+		ans.inflated.X2 = PCB->hidlib.dwg.X2;
 	else
 		ans.done |= _EAST;
 	if (ans.s && !boink_box(ans.s, &ans, RND_SOUTH))
-		ans.inflated.Y2 = PCB->hidlib.size_y;
+		ans.inflated.Y2 = PCB->hidlib.dwg.Y2;
 	else
 		ans.done |= _SOUTH;
 	if (ans.w && !boink_box(ans.w, &ans, RND_WEST))
@@ -2296,13 +2297,13 @@
 	case RND_EAST:
 		b.X1 = b.X2;
 		b.X2++;
-		if (b.X2 >= PCB->hidlib.size_x - AutoRouteParameters.bloat)
+		if (b.X2 >= PCB->hidlib.dwg.Y2 - AutoRouteParameters.bloat)
 			return;										/* off board edge */
 		break;
 	case RND_SOUTH:
 		b.Y1 = b.Y2;
 		b.Y2++;
-		if (b.Y2 >= PCB->hidlib.size_y - AutoRouteParameters.bloat)
+		if (b.Y2 >= PCB->hidlib.dwg.Y2 - AutoRouteParameters.bloat)
 			return;										/* off board edge */
 		break;
 	case RND_WEST:
@@ -2312,25 +2313,25 @@
 			return;										/* off board edge */
 		break;
 	case RND_NE:
-		if (b.Y1 <= AutoRouteParameters.bloat + 1 && b.X2 >= PCB->hidlib.size_x - AutoRouteParameters.bloat - 1)
+		if (b.Y1 <= AutoRouteParameters.bloat + 1 && b.X2 >= PCB->hidlib.dwg.X2 - AutoRouteParameters.bloat - 1)
 			return;										/* off board edge */
 		if (b.Y1 <= AutoRouteParameters.bloat + 1)
 			dir = RND_EAST;								/* north off board edge */
-		if (b.X2 >= PCB->hidlib.size_x - AutoRouteParameters.bloat - 1)
+		if (b.X2 >= PCB->hidlib.dwg.X2 - AutoRouteParameters.bloat - 1)
 			dir = RND_NORTH;							/* east off board edge */
 		break;
 	case RND_SE:
-		if (b.Y2 >= PCB->hidlib.size_y - AutoRouteParameters.bloat - 1 && b.X2 >= PCB->hidlib.size_x - AutoRouteParameters.bloat - 1)
+		if (b.Y2 >= PCB->hidlib.dwg.Y2 - AutoRouteParameters.bloat - 1 && b.X2 >= PCB->hidlib.dwg.X2 - AutoRouteParameters.bloat - 1)
 			return;										/* off board edge */
-		if (b.Y2 >= PCB->hidlib.size_y - AutoRouteParameters.bloat - 1)
+		if (b.Y2 >= PCB->hidlib.dwg.Y2 - AutoRouteParameters.bloat - 1)
 			dir = RND_EAST;								/* south off board edge */
-		if (b.X2 >= PCB->hidlib.size_x - AutoRouteParameters.bloat - 1)
+		if (b.X2 >= PCB->hidlib.dwg.X2 - AutoRouteParameters.bloat - 1)
 			dir = RND_SOUTH;							/* east off board edge */
 		break;
 	case RND_SW:
-		if (b.Y2 >= PCB->hidlib.size_y - AutoRouteParameters.bloat - 1 && b.X1 <= AutoRouteParameters.bloat + 1)
+		if (b.Y2 >= PCB->hidlib.dwg.Y2 - AutoRouteParameters.bloat - 1 && b.X1 <= AutoRouteParameters.bloat + 1)
 			return;										/* off board edge */
-		if (b.Y2 >= PCB->hidlib.size_y - AutoRouteParameters.bloat - 1)
+		if (b.Y2 >= PCB->hidlib.dwg.Y2 - AutoRouteParameters.bloat - 1)
 			dir = RND_WEST;								/* south off board edge */
 		if (b.X1 <= AutoRouteParameters.bloat + 1)
 			dir = RND_SOUTH;							/* west off board edge */
Index: trunk/src_plugins/diag/integrity.c
===================================================================
--- trunk/src_plugins/diag/integrity.c	(revision 36979)
+++ trunk/src_plugins/diag/integrity.c	(revision 36980)
@@ -116,8 +116,8 @@
 	if ((subc->BoundingBox.X2 < 0) || (subc->BoundingBox.Y2 < 0))
 		rnd_message(RND_MSG_ERROR, CHK "subc #%ld is on negative coordinates; its bottom right corner is %$mm;%$mm\n", subc->ID, subc->BoundingBox.X2, subc->BoundingBox.Y2);
 
-	if ((subc->BoundingBox.X1 > PCB->hidlib.size_x) || (subc->BoundingBox.Y1 > PCB->hidlib.size_y))
-		rnd_message(RND_MSG_ERROR, CHK "subc #%ld is olost beyond board extents; its top left corner is %$mm;%$mm\n", subc->ID, subc->BoundingBox.X1, subc->BoundingBox.Y1);
+	if ((subc->BoundingBox.X1 > PCB->hidlib.dwg.X2) || (subc->BoundingBox.Y1 > PCB->hidlib.dwg.Y2))
+		rnd_message(RND_MSG_ERROR, CHK "subc #%ld is lost beyond board extents; its top left corner is %$mm;%$mm\n", subc->ID, subc->BoundingBox.X1, subc->BoundingBox.Y1);
 
 	if ((arefdes == NULL) && (subc->refdes == NULL))
 		return;
Index: trunk/src_plugins/dialogs/dlg_netlist.c
===================================================================
--- trunk/src_plugins/dialogs/dlg_netlist.c	(revision 36979)
+++ trunk/src_plugins/dialogs/dlg_netlist.c	(revision 36980)
@@ -416,10 +416,10 @@
 	if (netlist_ctx.active)
 		return; /* do not open another */
 
-	netlist_ctx.bb_prv.X1 = 0;
-	netlist_ctx.bb_prv.Y1 = 0;
-	netlist_ctx.bb_prv.X2 = pcb->hidlib.size_x;
-	netlist_ctx.bb_prv.Y2 = pcb->hidlib.size_y;
+	netlist_ctx.bb_prv.X1 = pcb->hidlib.dwg.X1;
+	netlist_ctx.bb_prv.Y1 = pcb->hidlib.dwg.Y1;
+	netlist_ctx.bb_prv.X2 = pcb->hidlib.dwg.X2;
+	netlist_ctx.bb_prv.Y2 = pcb->hidlib.dwg.Y2;
 	netlist_ctx.pcb = pcb;
 
 	RND_DAD_BEGIN_VBOX(netlist_ctx.dlg); /* layout */
Index: trunk/src_plugins/dialogs/dlg_pref_sizes.c
===================================================================
--- trunk/src_plugins/dialogs/dlg_pref_sizes.c	(revision 36979)
+++ trunk/src_plugins/dialogs/dlg_pref_sizes.c	(revision 36980)
@@ -48,8 +48,8 @@
 
 	if (tabdata->lock)
 		return;
-	RND_DAD_SET_VALUE(ctx->dlg_hid_ctx, tabdata->wwidth, crd, PCB->hidlib.size_x);
-	RND_DAD_SET_VALUE(ctx->dlg_hid_ctx, tabdata->wheight, crd, PCB->hidlib.size_y);
+	RND_DAD_SET_VALUE(ctx->dlg_hid_ctx, tabdata->wwidth, crd, rnd_dwg_get_size_x(&PCB->hidlib));
+	RND_DAD_SET_VALUE(ctx->dlg_hid_ctx, tabdata->wheight, crd, rnd_dwg_get_size_y(&PCB->hidlib));
 }
 
 /* Dialog box to actual board size */
@@ -59,8 +59,10 @@
 	DEF_TABDATA;
 
 	tabdata->lock++;
-	if ((PCB->hidlib.size_x != ctx->dlg[tabdata->wwidth].val.crd) || (PCB->hidlib.size_y != ctx->dlg[tabdata->wheight].val.crd)) {
-		pcb_board_resize(ctx->dlg[tabdata->wwidth].val.crd, ctx->dlg[tabdata->wheight].val.crd, 1);
+	if ((rnd_dwg_get_size_x(&PCB->hidlib) != ctx->dlg[tabdata->wwidth].val.crd) || (rnd_dwg_get_size_y(&PCB->hidlib) != ctx->dlg[tabdata->wheight].val.crd)) {
+		rnd_coord_t x1 = PCB->hidlib.dwg.X1, y1 = PCB->hidlib.dwg.Y1;
+		rnd_coord_t x2 = PCB->hidlib.dwg.X1 + ctx->dlg[tabdata->wwidth].val.crd, y2 = PCB->hidlib.dwg.Y2 + ctx->dlg[tabdata->wheight].val.crd;
+		pcb_board_resize(x1, y1, x2, y2, 1);
 		pcb_undo_inc_serial();
 	}
 	tabdata->lock--;
@@ -130,13 +132,13 @@
 			RND_DAD_COORD(ctx->dlg);
 				tabdata->wwidth = RND_DAD_CURRENT(ctx->dlg);
 				RND_DAD_MINMAX(ctx->dlg, RND_MM_TO_COORD(1), RND_MAX_COORD);
-				RND_DAD_DEFAULT_NUM(ctx->dlg, PCB->hidlib.size_x);
+				RND_DAD_DEFAULT_NUM(ctx->dlg, rnd_dwg_get_size_x(&PCB->hidlib));
 				RND_DAD_CHANGE_CB(ctx->dlg, pref_sizes_dlg2brd);
 			RND_DAD_LABEL(ctx->dlg, "Height=");
 			RND_DAD_COORD(ctx->dlg);
 				tabdata->wheight = RND_DAD_CURRENT(ctx->dlg);
 				RND_DAD_MINMAX(ctx->dlg, RND_MM_TO_COORD(1), RND_MAX_COORD);
-				RND_DAD_DEFAULT_NUM(ctx->dlg, PCB->hidlib.size_y);
+				RND_DAD_DEFAULT_NUM(ctx->dlg, rnd_dwg_get_size_y(&PCB->hidlib));
 				RND_DAD_CHANGE_CB(ctx->dlg, pref_sizes_dlg2brd);
 		RND_DAD_END(ctx->dlg);
 	RND_DAD_END(ctx->dlg);
Index: trunk/src_plugins/draw_fab/draw_fab.c
===================================================================
--- trunk/src_plugins/draw_fab/draw_fab.c	(revision 36979)
+++ trunk/src_plugins/draw_fab/draw_fab.c	(revision 36980)
@@ -196,7 +196,7 @@
 	PCB_END_LOOP;
 	if (!found) {
 		rnd_hid_set_line_width(gc, FAB_LINE_W);
-		text_at(info, gc, PCB->hidlib.size_x / 2, PCB->hidlib.size_y + RND_MIL_TO_COORD(20), 1, "Board outline is the centerline of this path");
+		text_at(info, gc, PCB->hidlib.dwg.X2 / 2, PCB->hidlib.dwg.Y2 + RND_MIL_TO_COORD(20), 1, "Board outline is the centerline of this path");
 	}
 }
 
@@ -308,18 +308,18 @@
 	}
 	if (!found) {
 		rnd_hid_set_line_width(gc, RND_MIL_TO_COORD(10));
-		rnd_render->draw_line(gc, 0, 0, PCB->hidlib.size_x, 0);
-		rnd_render->draw_line(gc, 0, 0, 0, PCB->hidlib.size_y);
-		rnd_render->draw_line(gc, PCB->hidlib.size_x, 0, PCB->hidlib.size_x, PCB->hidlib.size_y);
-		rnd_render->draw_line(gc, 0, PCB->hidlib.size_y, PCB->hidlib.size_x, PCB->hidlib.size_y);
+		rnd_render->draw_line(gc, PCB->hidlib.dwg.X1, PCB->hidlib.dwg.Y1, PCB->hidlib.dwg.X2, PCB->hidlib.dwg.Y1);
+		rnd_render->draw_line(gc, PCB->hidlib.dwg.X1, PCB->hidlib.dwg.Y1, PCB->hidlib.dwg.X1, PCB->hidlib.dwg.Y2);
+		rnd_render->draw_line(gc, PCB->hidlib.dwg.X2, PCB->hidlib.dwg.Y1, PCB->hidlib.dwg.X2, PCB->hidlib.dwg.Y2);
+		rnd_render->draw_line(gc, PCB->hidlib.dwg.X1, PCB->hidlib.dwg.Y2, PCB->hidlib.dwg.X2, PCB->hidlib.dwg.Y2);
 		/*FPrintOutline (); */
 		rnd_hid_set_line_width(gc, FAB_LINE_W);
 		text_at(info, gc, RND_MIL_TO_COORD(2000), yoff, 0,
-						"Maximum Dimensions: %f mils wide, %f mils high", RND_COORD_TO_MIL(PCB->hidlib.size_x), RND_COORD_TO_MIL(PCB->hidlib.size_y));
-		text_at(info, gc, PCB->hidlib.size_x / 2, PCB->hidlib.size_y + RND_MIL_TO_COORD(20), 1,
+						"Maximum Dimensions: %f mils wide, %f mils high", RND_COORD_TO_MIL(rnd_dwg_get_size_x(&PCB->hidlib)), RND_COORD_TO_MIL(rnd_dwg_get_size_y(&PCB->hidlib)));
+		text_at(info, gc, (PCB->hidlib.dwg.X1+PCB->hidlib.dwg.X2) / 2, PCB->hidlib.dwg.Y2 + RND_MIL_TO_COORD(20), 1,
 						"Board outline is the centerline of this %f mil"
 						" rectangle - 0,0 to %f,%f mils",
-						RND_COORD_TO_MIL(FAB_LINE_W), RND_COORD_TO_MIL(PCB->hidlib.size_x), RND_COORD_TO_MIL(PCB->hidlib.size_y));
+						RND_COORD_TO_MIL(FAB_LINE_W), RND_COORD_TO_MIL(PCB->hidlib.dwg.X2), RND_COORD_TO_MIL(PCB->hidlib.dwg.Y2));
 	}
 	yoff -= TEXT_LINE;
 
Index: trunk/src_plugins/export_c_draw/export_c_draw.c
===================================================================
--- trunk/src_plugins/export_c_draw/export_c_draw.c	(revision 36979)
+++ trunk/src_plugins/export_c_draw/export_c_draw.c	(revision 36980)
@@ -104,10 +104,10 @@
 	static int saved_layer_stack[PCB_MAX_LAYER];
 	rnd_hid_expose_ctx_t ctx;
 
-	ctx.view.X1 = 0;
-	ctx.view.Y1 = 0;
-	ctx.view.X2 = PCB->hidlib.size_x;
-	ctx.view.Y2 = PCB->hidlib.size_y;
+	ctx.view.X1 = PCB->hidlib.dwg.X1;
+	ctx.view.Y1 = PCB->hidlib.dwg.Y1;
+	ctx.view.X2 = PCB->hidlib.dwg.X2;
+	ctx.view.Y2 = PCB->hidlib.dwg.Y2;
 
 	f = the_file;
 
Index: trunk/src_plugins/export_debug/export_debug.c
===================================================================
--- trunk/src_plugins/export_debug/export_debug.c	(revision 36979)
+++ trunk/src_plugins/export_debug/export_debug.c	(revision 36980)
@@ -112,10 +112,10 @@
 	static int saved_layer_stack[PCB_MAX_LAYER];
 	rnd_hid_expose_ctx_t ctx;
 
-	ctx.view.X1 = 0;
-	ctx.view.Y1 = 0;
-	ctx.view.X2 = PCB->hidlib.size_x;
-	ctx.view.Y2 = PCB->hidlib.size_y;
+	ctx.view.X1 = PCB->hidlib.dwg.X1;
+	ctx.view.Y1 = PCB->hidlib.dwg.X1;
+	ctx.view.X2 = PCB->hidlib.dwg.X2;
+	ctx.view.Y2 = PCB->hidlib.dwg.Y2;
 
 	f = the_file;
 
Index: trunk/src_plugins/export_dxf/dxf.c
===================================================================
--- trunk/src_plugins/export_dxf/dxf.c	(revision 36979)
+++ trunk/src_plugins/export_dxf/dxf.c	(revision 36980)
@@ -215,10 +215,10 @@
 	static int saved_layer_stack[PCB_MAX_LAYER];
 	rnd_hid_expose_ctx_t hectx;
 
-	hectx.view.X1 = 0;
-	hectx.view.Y1 = 0;
-	hectx.view.X2 = PCB->hidlib.size_x;
-	hectx.view.Y2 = PCB->hidlib.size_y;
+	hectx.view.X1 = PCB->hidlib.dwg.X1;
+	hectx.view.Y1 = PCB->hidlib.dwg.Y1;
+	hectx.view.X2 = PCB->hidlib.dwg.X2;
+	hectx.view.Y2 = PCB->hidlib.dwg.Y2;
 
 	memcpy(saved_layer_stack, pcb_layer_stack, sizeof(pcb_layer_stack));
 
@@ -240,7 +240,7 @@
 	if (strcmp(name, "extmin") == 0)
 		fprintf(f, "10\n0\n20\n0\n30\n0\n");
 	else if (strcmp(name, "extmax") == 0)
-		rnd_fprintf(f, "10\n%mm\n20\n0\n30\n%mm\n", PCB->hidlib.size_x, PCB->hidlib.size_y);
+		rnd_fprintf(f, "10\n%mm\n20\n0\n30\n%mm\n", PCB->hidlib.dwg.X2, PCB->hidlib.dwg.Y2);
 	else if (strcmp(name, "layers") == 0) {
 		const char **s;
 		for(s = layer_names; *s != NULL; s++)
Index: trunk/src_plugins/export_dxf/dxf_draw.c
===================================================================
--- trunk/src_plugins/export_dxf/dxf_draw.c	(revision 36979)
+++ trunk/src_plugins/export_dxf/dxf_draw.c	(revision 36980)
@@ -25,7 +25,7 @@
  */
 
 #define TRX(x)   (x)
-#define TRY(y)   (PCB->hidlib.size_y - (y))
+#define TRY(y)   (PCB->hidlib.dwg.Y2 - (y))
 
 static void dxf_draw_handle(dxf_ctx_t *ctx)
 {
Index: trunk/src_plugins/export_excellon/excellon.c
===================================================================
--- trunk/src_plugins/export_excellon/excellon.c	(revision 36979)
+++ trunk/src_plugins/export_excellon/excellon.c	(revision 36980)
@@ -27,7 +27,7 @@
 static int exc_aperture_cnt;
 
 #define excellonDrX(pcb, x) ((rnd_coord_t) (x))
-#define excellonDrY(pcb, y) ((rnd_coord_t) ((pcb)->hidlib.size_y - (y)))
+#define excellonDrY(pcb, y) ((rnd_coord_t) ((pcb)->hidlib.dwg.Y2 - (y)))
 
 typedef struct {
 	const char *hdr1;
@@ -245,10 +245,10 @@
 	if (!excellon_cam.active)
 		pcb_hid_save_and_show_layer_ons(save_ons);
 
-	ctx.view.X1 = 0;
-	ctx.view.Y1 = 0;
-	ctx.view.X2 = PCB->hidlib.size_x;
-	ctx.view.Y2 = PCB->hidlib.size_y;
+	ctx.view.X1 = PCB->hidlib.dwg.X1;
+	ctx.view.Y1 = PCB->hidlib.dwg.Y1;
+	ctx.view.X2 = PCB->hidlib.dwg.X2;
+	ctx.view.Y2 = PCB->hidlib.dwg.Y2;
 
 	lastwidth = -1;
 	finding_apertures = 1;
Index: trunk/src_plugins/export_gcode/gcode.c
===================================================================
--- trunk/src_plugins/export_gcode/gcode.c	(revision 36979)
+++ trunk/src_plugins/export_gcode/gcode.c	(revision 36980)
@@ -110,7 +110,7 @@
 }
 
 #define TX(x) (x)
-#define TY_MIRROR(y) (gctx.pcb->hidlib.size_y - (y))
+#define TY_MIRROR(y) (gctx.pcb->hidlib.dwg.Y2 - (y))
 #define TY_NORMAL(y) (y)
 #define TY(y) (gctx.grp->ltype & PCB_LYT_BOTTOM ? TY_MIRROR(y) : TY_NORMAL(y))
 
Index: trunk/src_plugins/export_gerber/gerber.c
===================================================================
--- trunk/src_plugins/export_gerber/gerber.c	(revision 36979)
+++ trunk/src_plugins/export_gerber/gerber.c	(revision 36980)
@@ -56,7 +56,7 @@
 
 /* These are for films */
 #define gerberX(pcb, x) ((rnd_coord_t) (x))
-#define gerberY(pcb, y) ((rnd_coord_t) ((pcb)->hidlib.size_y - (y)))
+#define gerberY(pcb, y) ((rnd_coord_t) ((pcb)->hidlib.dwg.Y2 - (y)))
 #define gerberXOffset(pcb, x) ((rnd_coord_t) (x))
 #define gerberYOffset(pcb, y) ((rnd_coord_t) (-(y)))
 
@@ -371,10 +371,10 @@
 	lastgroup = -1;
 	lastcolor = -1;
 
-	ctx.view.X1 = 0;
-	ctx.view.Y1 = 0;
-	ctx.view.X2 = PCB->hidlib.size_x;
-	ctx.view.Y2 = PCB->hidlib.size_y;
+	ctx.view.X1 = PCB->hidlib.dwg.X1;
+	ctx.view.Y1 = PCB->hidlib.dwg.Y1;
+	ctx.view.X2 = PCB->hidlib.dwg.X2;
+	ctx.view.Y2 = PCB->hidlib.dwg.Y2;
 
 	pagecount = 1;
 	reset_apertures();
@@ -550,7 +550,7 @@
 		fprintf(f, "G04 For: %s *\r\n", pcb_author());
 
 		fprintf(f, "G04 Format: Gerber/RS-274X *\r\n");
-		rnd_fprintf(f, "G04 PCB-Dimensions: %[4] %[4] *\r\n", PCB->hidlib.size_x, PCB->hidlib.size_y);
+		rnd_fprintf(f, "G04 PCB-Dimensions: %[4] %[4] *\r\n", rnd_dwg_get_size_x(&PCB->hidlib), rnd_dwg_get_size_y(&PCB->hidlib));
 		fprintf(f, "G04 PCB-Coordinate-Origin: lower left *\r\n");
 
 		/* Unit and coord format */
@@ -611,10 +611,10 @@
 				rnd_hid_set_line_width(gc, conf_core.design.min_wid);
 			else
 				rnd_hid_set_line_width(gc, AUTO_OUTLINE_WIDTH);
-			rnd_render->draw_line(gc, 0, 0, PCB->hidlib.size_x, 0);
-			rnd_render->draw_line(gc, 0, 0, 0, PCB->hidlib.size_y);
-			rnd_render->draw_line(gc, PCB->hidlib.size_x, 0, PCB->hidlib.size_x, PCB->hidlib.size_y);
-			rnd_render->draw_line(gc, 0, PCB->hidlib.size_y, PCB->hidlib.size_x, PCB->hidlib.size_y);
+			rnd_render->draw_line(gc, PCB->hidlib.dwg.X1, PCB->hidlib.dwg.Y1, PCB->hidlib.dwg.X2, PCB->hidlib.dwg.Y1);
+			rnd_render->draw_line(gc, PCB->hidlib.dwg.X1, PCB->hidlib.dwg.Y1, PCB->hidlib.dwg.X1, PCB->hidlib.dwg.Y2);
+			rnd_render->draw_line(gc, PCB->hidlib.dwg.X2, PCB->hidlib.dwg.Y1, PCB->hidlib.dwg.X2, PCB->hidlib.dwg.Y2);
+			rnd_render->draw_line(gc, PCB->hidlib.dwg.X1, PCB->hidlib.dwg.Y2, PCB->hidlib.dwg.X2, PCB->hidlib.dwg.Y2);
 			rnd_hid_destroy_gc(gc);
 		}
 	}
Index: trunk/src_plugins/export_hpgl/export_hpgl.c
===================================================================
--- trunk/src_plugins/export_hpgl/export_hpgl.c	(revision 36979)
+++ trunk/src_plugins/export_hpgl/export_hpgl.c	(revision 36980)
@@ -107,10 +107,10 @@
 	static int saved_layer_stack[PCB_MAX_LAYER];
 	rnd_hid_expose_ctx_t ctx;
 
-	ctx.view.X1 = 0;
-	ctx.view.Y1 = 0;
-	ctx.view.X2 = PCB->hidlib.size_x;
-	ctx.view.Y2 = PCB->hidlib.size_y;
+	ctx.view.X1 = PCB->hidlib.dwg.X1;
+	ctx.view.Y1 = PCB->hidlib.dwg.Y1;
+	ctx.view.X2 = PCB->hidlib.dwg.X2;
+	ctx.view.Y2 = PCB->hidlib.dwg.Y2;
 
 	f = the_file;
 
Index: trunk/src_plugins/export_ipcd356/ipcd356.c
===================================================================
--- trunk/src_plugins/export_ipcd356/ipcd356.c	(revision 36979)
+++ trunk/src_plugins/export_ipcd356/ipcd356.c	(revision 36980)
@@ -188,7 +188,7 @@
 	line[41] = 'X';
 	fill_field_coord(ctx, line, 42, 48, t->cx, 1, "X coord");
 	line[49] = 'Y';
-	fill_field_coord(ctx, line, 50, 56, PCB->hidlib.size_y - t->cy, 1, "Y coord");
+	fill_field_coord(ctx, line, 50, 56, PCB->hidlib.dwg.Y2 - t->cy, 1, "Y coord");
 
 	line[57] = 'X';
 	fill_field_coord(ctx, line, 58, 61, t->width, 0, "width");
Index: trunk/src_plugins/export_openems/export_openems.c
===================================================================
--- trunk/src_plugins/export_openems/export_openems.c	(revision 36979)
+++ trunk/src_plugins/export_openems/export_openems.c	(revision 36980)
@@ -361,10 +361,10 @@
 	}
 	else {
 		/* rectangular board size */
-		rnd_fprintf(ctx->f, "outline_xy(1, 1) = 0; outline_xy(2, 1) = 0;\n");
-		rnd_fprintf(ctx->f, "outline_xy(1, 2) = %mm; outline_xy(2, 2) = 0;\n", ctx->pcb->hidlib.size_x);
-		rnd_fprintf(ctx->f, "outline_xy(1, 3) = %mm; outline_xy(2, 3) = %mm;\n", ctx->pcb->hidlib.size_x, -ctx->pcb->hidlib.size_y);
-		rnd_fprintf(ctx->f, "outline_xy(1, 4) = 0; outline_xy(2, 4) = %mm;\n", -ctx->pcb->hidlib.size_y);
+		rnd_fprintf(ctx->f, "outline_xy(1, 1) = %mm; outline_xy(2, 1) = %mm;\n", ctx->pcb->hidlib.dwg.X1, -ctx->pcb->hidlib.dwg.Y1);
+		rnd_fprintf(ctx->f, "outline_xy(1, 2) = %mm; outline_xy(2, 2) = %mm;\n", ctx->pcb->hidlib.dwg.X2, -ctx->pcb->hidlib.dwg.Y1);
+		rnd_fprintf(ctx->f, "outline_xy(1, 3) = %mm; outline_xy(2, 3) = %mm;\n", ctx->pcb->hidlib.dwg.X2, -ctx->pcb->hidlib.dwg.Y2);
+		rnd_fprintf(ctx->f, "outline_xy(1, 4) = %mm; outline_xy(2, 4) = %mm;\n", ctx->pcb->hidlib.dwg.X1, -ctx->pcb->hidlib.dwg.Y2);
 	}
 
 	/* create all substrate layers using this polygon*/
@@ -631,10 +631,10 @@
 	wctx.fmt_matlab = fmt_matlab;
 	ems_ctx = &wctx;
 
-	ctx.view.X1 = 0;
-	ctx.view.Y1 = 0;
-	ctx.view.X2 = PCB->hidlib.size_x;
-	ctx.view.Y2 = PCB->hidlib.size_y;
+	ctx.view.X1 = PCB->hidlib.dwg.X1;
+	ctx.view.Y1 = PCB->hidlib.dwg.Y1;
+	ctx.view.X2 = PCB->hidlib.dwg.X2;
+	ctx.view.Y2 = PCB->hidlib.dwg.Y2;
 
 	f = the_file;
 
Index: trunk/src_plugins/export_openems/mesh.c
===================================================================
--- trunk/src_plugins/export_openems/mesh.c	(revision 36979)
+++ trunk/src_plugins/export_openems/mesh.c	(revision 36980)
@@ -589,7 +589,7 @@
 
 	r = vtr0_alloc_append(&mesh->line[dir].dens, 1);
 	r->begin = mesh->line[dir].dens.array[vtr0_len(&mesh->line[dir].dens)-2].end;
-	r->end = (dir == PCB_MESH_HORIZONTAL) ? PCB->hidlib.size_y : PCB->hidlib.size_x;
+	r->end = (dir == PCB_MESH_HORIZONTAL) ? PCB->hidlib.dwg.Y2 : PCB->hidlib.dwg.X2;
 	r->data[0].c = mesh->dens_gap;
 
 
@@ -762,7 +762,7 @@
 	mesh_trace("\n");
 
 	mesh_trace("%s result:\n", dir == PCB_MESH_HORIZONTAL ? "horizontal" : "vertical");
-	end = (dir == PCB_MESH_HORIZONTAL) ? PCB->hidlib.size_x : PCB->hidlib.size_y;
+	end = (dir == PCB_MESH_HORIZONTAL) ? PCB->hidlib.dwg.X2 : PCB->hidlib.dwg.Y2;
 	for(n = 0; n < vtc0_len(&mesh->line[dir].result); n++) {
 		mesh_trace(" %mm", mesh->line[dir].result.array[n]);
 		mesh_draw_line(mesh, dir, mesh->line[dir].result.array[n], 0, end, RND_MM_TO_COORD(0.03));
@@ -776,9 +776,9 @@
 {
 	int n;
 	rnd_layergrp_id_t gid;
-	rnd_coord_t y0 = PCB->hidlib.size_y/3, y = y0, y2;
-	rnd_coord_t xl = PCB->hidlib.size_x/5; /* board left */
-	rnd_coord_t xr = PCB->hidlib.size_x/5*3; /* board right */
+	rnd_coord_t y0 = PCB->hidlib.dwg.Y2/3, y = y0, y2;
+	rnd_coord_t xl = PCB->hidlib.dwg.X2/5; /* board left */
+	rnd_coord_t xr = PCB->hidlib.dwg.X2/5*3; /* board right */
 	rnd_coord_t spen = RND_MM_TO_COORD(0.3), cpen = RND_MM_TO_COORD(0.2), mpen = RND_MM_TO_COORD(0.03);
 	int mag = 2;
 
@@ -804,7 +804,7 @@
 	for(n = 0; n < vtc0_len(&mesh->line[PCB_MESH_Z].result); n++) {
 		rnd_coord_t y = y0+mesh->line[PCB_MESH_Z].result.array[n]*mag;
 		mesh_trace(" %mm", y);
-		pcb_line_new(mesh->ui_layer_z, 0, y, PCB->hidlib.size_x, y, mpen, 0, pcb_no_flags());
+		pcb_line_new(mesh->ui_layer_z, 0, y, PCB->hidlib.dwg.X2, y, mpen, 0, pcb_no_flags());
 	}
 	mesh_trace("\n");
 	return 0;
@@ -926,7 +926,7 @@
 	/* right edge, after the last known line */
 	if (!mesh->noimpl) {
 		c1 = mesh->line[dir].edge.array[vtc0_len(&mesh->line[dir].edge)-1];
-		c2 = (dir == PCB_MESH_HORIZONTAL) ? PCB->hidlib.size_y : PCB->hidlib.size_x;
+		c2 = (dir == PCB_MESH_HORIZONTAL) ? PCB->hidlib.dwg.Y2 : PCB->hidlib.dwg.X2;
 		mesh_find_range(&mesh->line[dir].dens, (c1+c2)/2, &d, &d1, &d2);
 		if (mesh->smooth)
 			mesh_auto_add_smooth(&mesh->line[dir].result, c1, c2, d1, d, d2);
Index: trunk/src_plugins/export_openems/openems_xml.c
===================================================================
--- trunk/src_plugins/export_openems/openems_xml.c	(revision 36979)
+++ trunk/src_plugins/export_openems/openems_xml.c	(revision 36980)
@@ -107,10 +107,10 @@
 	}
 	else {
 		/* rectangular board size */
-		rnd_fprintf(ctx->f, "            <Vertex X1='%mm' X2='%mm'/>\n", 0, 0);
-		rnd_fprintf(ctx->f, "            <Vertex X1='%mm' X2='%mm'/>\n", ctx->pcb->hidlib.size_x, 0);
-		rnd_fprintf(ctx->f, "            <Vertex X1='%mm' X2='%mm'/>\n", ctx->pcb->hidlib.size_x, -ctx->pcb->hidlib.size_y);
-		rnd_fprintf(ctx->f, "            <Vertex X1='%mm' X2='%mm'/>\n", 0, -ctx->pcb->hidlib.size_y);
+		rnd_fprintf(ctx->f, "            <Vertex X1='%mm' X2='%mm'/>\n", ctx->pcb->hidlib.dwg.X1, -ctx->pcb->hidlib.dwg.Y1);
+		rnd_fprintf(ctx->f, "            <Vertex X1='%mm' X2='%mm'/>\n", ctx->pcb->hidlib.dwg.X2, -ctx->pcb->hidlib.dwg.Y1);
+		rnd_fprintf(ctx->f, "            <Vertex X1='%mm' X2='%mm'/>\n", ctx->pcb->hidlib.dwg.X2, -ctx->pcb->hidlib.dwg.Y2);
+		rnd_fprintf(ctx->f, "            <Vertex X1='%mm' X2='%mm'/>\n", ctx->pcb->hidlib.dwg.X1, -ctx->pcb->hidlib.dwg.Y2);
 	}
 	rnd_fprintf(ctx->f, "          </LinPoly>\n");
 	return 0;
@@ -147,10 +147,10 @@
 	int err = 0;
 
 
-	ectx.view.X1 = 0;
-	ectx.view.Y1 = 0;
-	ectx.view.X2 = ctx->pcb->hidlib.size_x;
-	ectx.view.Y2 = ctx->pcb->hidlib.size_y;
+	ectx.view.X1 = ctx->pcb->hidlib.dwg.X1;
+	ectx.view.Y1 = ctx->pcb->hidlib.dwg.Y2;
+	ectx.view.X2 = ctx->pcb->hidlib.dwg.X2;
+	ectx.view.Y2 = ctx->pcb->hidlib.dwg.Y2;
 
 	rnd_app.expose_main(&openems_hid, &ectx, NULL);
 	openems_wr_xml_layergrp_end(ctx);
Index: trunk/src_plugins/export_openscad/export_openscad.c
===================================================================
--- trunk/src_plugins/export_openscad/export_openscad.c	(revision 36979)
+++ trunk/src_plugins/export_openscad/export_openscad.c	(revision 36980)
@@ -149,10 +149,10 @@
 	static int saved_layer_stack[PCB_MAX_LAYER];
 	rnd_hid_expose_ctx_t ctx;
 
-	ctx.view.X1 = 0;
-	ctx.view.Y1 = 0;
-	ctx.view.X2 = PCB->hidlib.size_x;
-	ctx.view.Y2 = PCB->hidlib.size_y;
+	ctx.view.X1 = PCB->hidlib.dwg.X1;
+	ctx.view.Y1 = PCB->hidlib.dwg.Y1;
+	ctx.view.X2 = PCB->hidlib.dwg.X2;
+	ctx.view.Y2 = PCB->hidlib.dwg.Y2;
 
 	f = the_file;
 
Index: trunk/src_plugins/export_openscad/scad_draw.c
===================================================================
--- trunk/src_plugins/export_openscad/scad_draw.c	(revision 36979)
+++ trunk/src_plugins/export_openscad/scad_draw.c	(revision 36980)
@@ -30,7 +30,7 @@
 
 
 #define TRX_(x) (x)
-#define TRY_(y) (PCB->hidlib.size_y - (y))
+#define TRY_(y) (PCB->hidlib.dwg.Y2 - (y))
 
 #define TRX(x)
 #define TRY(y) y = TRY_(y)
Index: trunk/src_plugins/export_png/png.c
===================================================================
--- trunk/src_plugins/export_png/png.c	(revision 36979)
+++ trunk/src_plugins/export_png/png.c	(revision 36980)
@@ -373,10 +373,10 @@
 
 	png_f = the_file;
 
-	region.X1 = 0;
-	region.Y1 = 0;
-	region.X2 = PCB->hidlib.size_x;
-	region.Y2 = PCB->hidlib.size_y;
+	region.X1 = PCB->hidlib.dwg.X1;
+	region.Y1 = PCB->hidlib.dwg.Y1;
+	region.X2 = PCB->hidlib.dwg.X2;
+	region.Y2 = PCB->hidlib.dwg.Y2;
 
 	png_options = options;
 	if (options[HA_only_visible].lng)
Index: trunk/src_plugins/export_ps/eps.c
===================================================================
--- trunk/src_plugins/export_ps/eps.c	(revision 36979)
+++ trunk/src_plugins/export_ps/eps.c	(revision 36980)
@@ -167,10 +167,10 @@
 
 	options_ = options;
 
-	region.X1 = 0;
-	region.Y1 = 0;
-	region.X2 = PCB->hidlib.size_x;
-	region.Y2 = PCB->hidlib.size_y;
+	region.X1 = PCB->hidlib.dwg.X1;
+	region.Y1 = PCB->hidlib.dwg.Y1;
+	region.X2 = PCB->hidlib.dwg.X2;
+	region.Y2 = PCB->hidlib.dwg.Y2;
 
 	if (options[HA_only_visible].lng)
 		bnds = pcb_data_bbox(&tmp, PCB->Data, rnd_false);
Index: trunk/src_plugins/export_ps/ps.c
===================================================================
--- trunk/src_plugins/export_ps/ps.c	(revision 36979)
+++ trunk/src_plugins/export_ps/ps.c	(revision 36980)
@@ -409,10 +409,10 @@
 	/* reset static vars */
 	rnd_ps_use_gc(&global.ps, NULL);
 
-	global.exps.view.X1 = 0;
-	global.exps.view.Y1 = 0;
-	global.exps.view.X2 = PCB->hidlib.size_x;
-	global.exps.view.Y2 = PCB->hidlib.size_y;
+	global.exps.view.X1 = PCB->hidlib.dwg.X1;
+	global.exps.view.Y1 = PCB->hidlib.dwg.Y1;
+	global.exps.view.X2 = PCB->hidlib.dwg.X2;
+	global.exps.view.Y2 = PCB->hidlib.dwg.Y2;
 
 	global.had_page = 0;
 
@@ -600,7 +600,7 @@
 		   If users don't want to make smaller boards, or use fewer drill
 		   sizes, they can always ignore this sheet. */
 		if (PCB_LAYER_IS_FAB(flags, purpi)) {
-			rnd_coord_t natural = boffset - RND_MIL_TO_COORD(500) - PCB->hidlib.size_y / 2;
+			rnd_coord_t natural = boffset - RND_MIL_TO_COORD(500) - (PCB->hidlib.dwg.Y1 + PCB->hidlib.dwg.Y2) / 2;
 			rnd_coord_t needed = pcb_stub_draw_fab_overhang();
 			rnd_fprintf(global.ps.outf, "%% PrintFab overhang natural %mi, needed %mi\n", natural, needed);
 			if (needed > natural)
Index: trunk/src_plugins/export_stat/stat.c
===================================================================
--- trunk/src_plugins/export_stat/stat.c	(revision 36979)
+++ trunk/src_plugins/export_stat/stat.c	(revision 36980)
@@ -339,8 +339,8 @@
 		height = bb.Y2 - bb.Y1;
 	}
 	else {
-		width = PCB->hidlib.size_x;
-		height = PCB->hidlib.size_y;
+		width = rnd_dwg_get_size_x(&PCB->hidlib);
+		height = rnd_dwg_get_size_y(&PCB->hidlib);
 	}
 
 	fprintf(f, "	ha:board {\n");
Index: trunk/src_plugins/export_stl/export_stl.c
===================================================================
--- trunk/src_plugins/export_stl/export_stl.c	(revision 36979)
+++ trunk/src_plugins/export_stl/export_stl.c	(revision 36980)
@@ -555,9 +555,9 @@
 	}
 
 	if (options[HA_zcent].lng)
-		stl_hid_export_to_file(f, options, PCB->hidlib.size_y, -thick/2, +thick/2, fmt);
+		stl_hid_export_to_file(f, options, PCB->hidlib.dwg.Y2, -thick/2, +thick/2, fmt);
 	else
-		stl_hid_export_to_file(f, options, PCB->hidlib.size_y, 0, thick, fmt);
+		stl_hid_export_to_file(f, options, PCB->hidlib.dwg.Y2, 0, thick, fmt);
 
 	fclose(f);
 	pcb_cam_end(&cam);
Index: trunk/src_plugins/export_svg/svg.c
===================================================================
--- trunk/src_plugins/export_svg/svg.c	(revision 36979)
+++ trunk/src_plugins/export_svg/svg.c	(revision 36980)
@@ -160,10 +160,10 @@
 	static int saved_layer_stack[PCB_MAX_LAYER];
 	rnd_hid_expose_ctx_t ctx;
 
-	ctx.view.X1 = 0;
-	ctx.view.Y1 = 0;
-	ctx.view.X2 = PCB->hidlib.size_x;
-	ctx.view.Y2 = PCB->hidlib.size_y;
+	ctx.view.X1 = PCB->hidlib.dwg.X1;
+	ctx.view.Y1 = PCB->hidlib.dwg.Y1;
+	ctx.view.X2 = PCB->hidlib.dwg.X2;
+	ctx.view.Y2 = PCB->hidlib.dwg.Y2;
 
 	pctx->outf = the_file;
 
Index: trunk/src_plugins/export_xy/xy.c
===================================================================
--- trunk/src_plugins/export_xy/xy.c	(revision 36979)
+++ trunk/src_plugins/export_xy/xy.c	(revision 36980)
@@ -219,9 +219,9 @@
 {
 	/* default: bottom left of the drawing area */
 	ctx->ox = 0;
-	ctx->oy = PCB->hidlib.size_y;
-	ctx->bottom_ox = PCB->hidlib.size_x;
-	ctx->bottom_oy = PCB->hidlib.size_y;
+	ctx->oy = PCB->hidlib.dwg.Y2;
+	ctx->bottom_ox = PCB->hidlib.dwg.X2;
+	ctx->bottom_oy = PCB->hidlib.dwg.Y2;
 
 	find_origin_(format_name, "", &ctx->ox, &ctx->oy);
 	find_origin_(format_name, "bottom-", &ctx->bottom_ox, &ctx->bottom_oy);
@@ -388,12 +388,12 @@
 	}
 	if (strncmp(*input, "boardw%", 7) == 0) {
 		*input += 7;
-		rnd_append_printf(s, "%m+%mN", xy_unit->allow, PCB->hidlib.size_x);
+		rnd_append_printf(s, "%m+%mN", xy_unit->allow, PCB->hidlib.dwg.X2);
 		return 0;
 	}
 	if (strncmp(*input, "boardh%", 7) == 0) {
 		*input += 7;
-		rnd_append_printf(s, "%m+%mN", xy_unit->allow, PCB->hidlib.size_y);
+		rnd_append_printf(s, "%m+%mN", xy_unit->allow, PCB->hidlib.dwg.Y2);
 		return 0;
 	}
 	if (strncmp(*input, "subc.", 5) == 0) {
Index: trunk/src_plugins/fontmode/fontmode.c
===================================================================
--- trunk/src_plugins/fontmode/fontmode.c	(revision 36979)
+++ trunk/src_plugins/fontmode/fontmode.c	(revision 36980)
@@ -329,8 +329,8 @@
 	rnd_conf_set_design("design/text_font_id", "%s", "0");
 
 
-	pcb->hidlib.size_x = CELL_SIZE * 18;
-	pcb->hidlib.size_y = CELL_SIZE * ((PCB_MAX_FONTPOSITION + 15) / 16 + 2);
+	pcb->hidlib.dwg.X2 = CELL_SIZE * 18;
+	pcb->hidlib.dwg.Y2 = CELL_SIZE * ((PCB_MAX_FONTPOSITION + 15) / 16 + 2);
 	pcb->hidlib.grid = RND_MIL_TO_COORD(5);
 
 	/* create the layer stack and logical layers */
@@ -360,11 +360,11 @@
 
 	for (l = 0; l < 16; l++) {
 		int x = (l + 1) * CELL_SIZE;
-		pcb_line_new_merge(lgrid, x, 0, x, pcb->hidlib.size_y, RND_MIL_TO_COORD(1), RND_MIL_TO_COORD(1), pcb_no_flags());
+		pcb_line_new_merge(lgrid, x, 0, x, pcb->hidlib.dwg.Y2, RND_MIL_TO_COORD(1), RND_MIL_TO_COORD(1), pcb_no_flags());
 	}
 	for (l = 0; l <= PCB_MAX_FONTPOSITION / 16 + 1; l++) {
 		int y = (l + 1) * CELL_SIZE;
-		pcb_line_new_merge(lgrid, 0, y, pcb->hidlib.size_x, y, RND_MIL_TO_COORD(1), RND_MIL_TO_COORD(1), pcb_no_flags());
+		pcb_line_new_merge(lgrid, 0, y, pcb->hidlib.dwg.X2, y, RND_MIL_TO_COORD(1), RND_MIL_TO_COORD(1), pcb_no_flags());
 	}
 	RND_ACT_IRES(0);
 	return 0;
Index: trunk/src_plugins/import_ipcd356/ipcd356.c
===================================================================
--- trunk/src_plugins/import_ipcd356/ipcd356.c	(revision 36979)
+++ trunk/src_plugins/import_ipcd356/ipcd356.c	(revision 36980)
@@ -275,8 +275,8 @@
 		}
 	}
 
-	y = pcb->hidlib.size_y - tf->cy;
-	if ((y < 0) || (y > pcb->hidlib.size_y) || (tf->cx < 0) || (tf->cx > pcb->hidlib.size_x))
+	y = pcb->hidlib.dwg.Y2 - tf->cy;
+	if ((y < pcb->hidlib.dwg.Y1) || (y > pcb->hidlib.dwg.Y2) || (tf->cx < pcb->hidlib.dwg.X1) || (tf->cx > pcb->hidlib.dwg.X2))
 		rnd_message(RND_MSG_WARNING, "Test feature ended up out of the board extents in %s:%ld - board too small please use autocrop()\n", fn, lineno);
 	ps = pcb_pstk_new_from_shape(data, tf->cx, y, tf->hole, tf->is_plated, conf_core.design.bloat, sh);
 
Index: trunk/src_plugins/io_altium/pcbdoc.c
===================================================================
--- trunk/src_plugins/io_altium/pcbdoc.c	(revision 36979)
+++ trunk/src_plugins/io_altium/pcbdoc.c	(revision 36980)
@@ -130,7 +130,7 @@
 
 static rnd_coord_t conv_coordy_field(rctx_t *rctx, altium_field_t *field)
 {
-	return rctx->pcb->hidlib.size_y - conv_coord_field(field);
+	return rctx->pcb->hidlib.dwg.Y2 - conv_coord_field(field);
 }
 
 static double conv_double_field(altium_field_t *field)
@@ -456,10 +456,10 @@
 	for(n = 37; n <= 52; n++) {
 		if (rctx->midly[n] != NULL) {
 			pcb_poly_t *poly = pcb_poly_new(rctx->midly[n], 0, pcb_flag_make(PCB_FLAG_CLEARPOLY));
-			pcb_poly_point_new(poly, 0, 0);
-			pcb_poly_point_new(poly, rctx->pcb->hidlib.size_x, 0);
-			pcb_poly_point_new(poly, rctx->pcb->hidlib.size_x, rctx->pcb->hidlib.size_y);
-			pcb_poly_point_new(poly, 0, rctx->pcb->hidlib.size_y);
+			pcb_poly_point_new(poly, rctx->pcb->hidlib.dwg.X1, rctx->pcb->hidlib.dwg.Y1);
+			pcb_poly_point_new(poly, rctx->pcb->hidlib.dwg.X2, rctx->pcb->hidlib.dwg.Y1);
+			pcb_poly_point_new(poly, rctx->pcb->hidlib.dwg.X2, rctx->pcb->hidlib.dwg.Y2);
+			pcb_poly_point_new(poly, rctx->pcb->hidlib.dwg.X1, rctx->pcb->hidlib.dwg.Y2);
 			pcb_add_poly_on_layer(rctx->midly[n], poly);
 			plane[n-37] = poly;
 			pcb_attribute_put(&(poly->Attributes), "altium::plane", "yes");
@@ -494,8 +494,8 @@
 	for(rec = gdl_first(&rctx->tree.rec[altium_kw_record_board]); rec != NULL; rec = gdl_next(&rctx->tree.rec[altium_kw_record_board], rec)) {
 		for(field = gdl_first(&rec->fields); field != NULL; field = gdl_next(&rec->fields, field)) {
 			switch(field->type) {
-				case altium_kw_field_sheetheight: rctx->pcb->hidlib.size_x = conv_coord_field(field); break;
-				case altium_kw_field_sheetwidth:  rctx->pcb->hidlib.size_y = conv_coord_field(field); break;
+				case altium_kw_field_sheetheight: rctx->pcb->hidlib.dwg.X2 = conv_coord_field(field); break;
+				case altium_kw_field_sheetwidth:  rctx->pcb->hidlib.dwg.Y2 = conv_coord_field(field); break;
 				case altium_kw_field_togglelayers:
 					{
 						int len;
@@ -512,11 +512,11 @@
 					/* vx[0-4] and vy[0-4] */
 					if ((tolower(field->key[0]) == 'v') && isdigit(field->key[2]) && (field->key[3] == 0)) {
 						if (tolower(field->key[1]) == 'x') {
-							BUMP_COORD(rctx->pcb->hidlib.size_x, conv_coord_field(field));
+							BUMP_COORD(rctx->pcb->hidlib.dwg.X2, conv_coord_field(field));
 							rctx->has_bnd |= 1;
 						}
 						if (tolower(field->key[1]) == 'y') {
-							BUMP_COORD(rctx->pcb->hidlib.size_y, conv_coord_field(field));
+							BUMP_COORD(rctx->pcb->hidlib.dwg.Y2, conv_coord_field(field));
 							rctx->has_bnd |= 2;
 						}
 					}
@@ -542,7 +542,7 @@
 	}
 
 	if (rctx->has_bnd != 3)
-		rctx->pcb->hidlib.size_x = rctx->pcb->hidlib.size_y = 0;
+		rctx->pcb->hidlib.dwg.X2 = rctx->pcb->hidlib.dwg.Y2 = 0;
 
 	/*** create the layer stack (copper only) ***/
 
@@ -1825,11 +1825,14 @@
 	if (rctx.has_bnd != 3) {
 		rnd_box_t b;
 		pcb_data_bbox(&b, rctx.pcb->Data, 0);
-		rctx.pcb->hidlib.size_x = b.X2-b.X1;
-		rctx.pcb->hidlib.size_y = b.Y2-b.Y1;
+		rctx.pcb->hidlib.dwg.X1 = b.X1;
+		rctx.pcb->hidlib.dwg.Y1 = b.Y1;
+		rctx.pcb->hidlib.dwg.X2 = b.X2;
+		rctx.pcb->hidlib.dwg.Y2 = b.Y2;
+/* autocrop-like move, pre-librnd4:
 		pcb_data_move(rctx.pcb->Data, -b.X1, -b.Y1, 0);
 		rctx.moved_x = -b.X1;
-		rctx.moved_y = -b.Y1;
+		rctx.moved_y = -b.Y1;*/
 		rnd_message(RND_MSG_ERROR, "Board without contour or body - can not determine real size\n");
 	}
 
Index: trunk/src_plugins/io_autotrax/read.c
===================================================================
--- trunk/src_plugins/io_autotrax/read.c	(revision 36979)
+++ trunk/src_plugins/io_autotrax/read.c	(revision 36980)
@@ -1155,8 +1155,8 @@
 	}
 
 	if (box != NULL) {
-		Ptr->hidlib.size_x = box->X2;
-		Ptr->hidlib.size_y = box->Y2;
+		Ptr->hidlib.dwg.X2 = box->X2;
+		Ptr->hidlib.dwg.Y2 = box->Y2;
 	}
 	else
 		rnd_message(RND_MSG_ERROR, "Can not determine board extents - empty board?\n");
Index: trunk/src_plugins/io_autotrax/write.c
===================================================================
--- trunk/src_plugins/io_autotrax/write.c	(revision 36979)
+++ trunk/src_plugins/io_autotrax/write.c	(revision 36980)
@@ -221,7 +221,7 @@
 TODO("add checks for thermals: only gnd/pwr can have them, warn for others")
 
 	rnd_fprintf(ctx->f, "%.0ml %.0ml %.0ml %.0ml %d %.0ml 1 %d\r\n",
-		x+dx, PCB->hidlib.size_y - (y+dy), w, h,
+		x+dx, PCB->hidlib.dwg.Y2 - (y+dy), w, h,
 		ashape, drill_dia, alayer);
 
 	fputs(name, ctx->f);
@@ -247,7 +247,7 @@
 static int wrax_line(wctx_t *ctx, pcb_line_t *line, rnd_cardinal_t layer, rnd_coord_t dx, rnd_coord_t dy)
 {
 	int user_routed = 1;
-	rnd_fprintf(ctx->f, "%.0ml %.0ml %.0ml %.0ml %.0ml %d %d\r\n", line->Point1.X+dx, PCB->hidlib.size_y - (line->Point1.Y+dy), line->Point2.X+dx, PCB->hidlib.size_y - (line->Point2.Y+dy), line->Thickness, layer, user_routed);
+	rnd_fprintf(ctx->f, "%.0ml %.0ml %.0ml %.0ml %.0ml %d %d\r\n", line->Point1.X+dx, PCB->hidlib.dwg.Y2 - (line->Point1.Y+dy), line->Point2.X+dx, PCB->hidlib.dwg.Y2 - (line->Point2.Y+dy), line->Thickness, layer, user_routed);
 	return 0;
 }
 
@@ -255,7 +255,7 @@
 static int wrax_pline_segment(wctx_t *ctx, rnd_coord_t x1, rnd_coord_t y1, rnd_coord_t x2, rnd_coord_t y2, rnd_coord_t Thickness, rnd_cardinal_t layer)
 {
 	int user_routed = 1;
-	rnd_fprintf(ctx->f, "FT\r\n%.0ml %.0ml %.0ml %.0ml %.0ml %d %d\r\n", x1, PCB->hidlib.size_y - y1, x2, PCB->hidlib.size_y - y2, Thickness, layer, user_routed);
+	rnd_fprintf(ctx->f, "FT\r\n%.0ml %.0ml %.0ml %.0ml %.0ml %d %d\r\n", x1, PCB->hidlib.dwg.Y2 - y1, x2, PCB->hidlib.dwg.Y2 - y2, Thickness, layer, user_routed);
 	return 0;
 }
 
@@ -340,7 +340,7 @@
 	else {
 		radius = arc->Width;
 	}
-	rnd_fprintf(ctx->f, "%.0ml %.0ml %.0ml %d %.0ml %d\r\n", arc->X+dx, PCB->hidlib.size_y - (arc->Y+dy), radius, pcb_rnd_arc_to_autotrax_segments(arc->StartAngle, arc->Delta), arc->Thickness, current_layer);
+	rnd_fprintf(ctx->f, "%.0ml %.0ml %.0ml %d %.0ml %d\r\n", arc->X+dx, PCB->hidlib.dwg.Y2 - (arc->Y+dy), radius, pcb_rnd_arc_to_autotrax_segments(arc->StartAngle, arc->Delta), arc->Thickness, current_layer);
 	return 0;
 }
 
@@ -479,7 +479,7 @@
 				else if (direction == 0) /*normal text */
 					rotation = 0;
 
-				rnd_fprintf(ctx->f, "%.0ml %.0ml %.0ml %d %.0ml %d\r\n", text->X+dx, PCB->hidlib.size_y - (text->Y+dy), textHeight, rotation + autotrax_mirrored, strokeThickness, current_layer);
+				rnd_fprintf(ctx->f, "%.0ml %.0ml %.0ml %d %.0ml %d\r\n", text->X+dx, PCB->hidlib.dwg.Y2 - (text->Y+dy), textHeight, rotation + autotrax_mirrored, strokeThickness, current_layer);
 				for(index = 0; index < 32; index++) {
 					if (text->TextString[index] == '\0')
 						index = 32;
@@ -516,7 +516,7 @@
 TODO("rename these variables to something more expressive")
 TODO("instead of hardwiring coords, just read existing dyntex coords")
 	xPos = (box->X1 + box->X2) / 2;
-	yPos = PCB->hidlib.size_y - (box->Y1 - text_offset);
+	yPos = PCB->hidlib.dwg.Y2 - (box->Y1 - text_offset);
 	yPos2 = yPos - RND_MIL_TO_COORD(200);
 	yPos3 = yPos2 - RND_MIL_TO_COORD(200);
 
@@ -590,7 +590,7 @@
 					if (maxy < polygon->Points[i].Y)
 						maxy = polygon->Points[i].Y;
 				}
-				rnd_fprintf(ctx->f, "%cF\r\n%.0ml %.0ml %.0ml %.0ml %d\r\n", (in_subc ? 'C' : 'F'), minx+dx, PCB->hidlib.size_y - (miny+dy), maxx+dx, PCB->hidlib.size_y - (maxy+dy), current_layer);
+				rnd_fprintf(ctx->f, "%cF\r\n%.0ml %.0ml %.0ml %.0ml %d\r\n", (in_subc ? 'C' : 'F'), minx+dx, PCB->hidlib.dwg.Y2 - (miny+dy), maxx+dx, PCB->hidlib.dwg.Y2 - (maxy+dy), current_layer);
 
 				local_flag |= 1;
 /* here we need to test for non rectangular polygons to flag imperfect export to easy/autotrax
@@ -695,7 +695,7 @@
 	fputs("PCB FILE 4\r\n", FP); /*autotrax header */
 
 	/* we sort out if the layout dimensions exceed the autotrax maxima */
-	if (RND_COORD_TO_MIL(PCB->hidlib.size_x) > max_width_mil || RND_COORD_TO_MIL(PCB->hidlib.size_y) > max_height_mil) {
+	if (RND_COORD_TO_MIL(PCB->hidlib.dwg.X2) > max_width_mil || RND_COORD_TO_MIL(PCB->hidlib.dwg.Y2) > max_height_mil) {
 		rnd_message(RND_MSG_ERROR, "Layout size exceeds protel autotrax 32000 mil x 32000 mil maximum.");
 		return -1;
 	}
Index: trunk/src_plugins/io_dsn/read.c
===================================================================
--- trunk/src_plugins/io_dsn/read.c	(revision 36979)
+++ trunk/src_plugins/io_dsn/read.c	(revision 36980)
@@ -506,8 +506,8 @@
 	if ((ctx->bbox.X1 < 0) || (ctx->bbox.Y1 < 0))
 		rnd_message(RND_MSG_WARNING, "Negative coordinates on input - you may want to execute autocrop()\n");
 
-	ctx->pcb->hidlib.size_x = ctx->bbox.X2 - ctx->bbox.X1;
-	ctx->pcb->hidlib.size_y = ctx->bbox.Y2 - ctx->bbox.Y1;
+	ctx->pcb->hidlib.dwg.X2 = ctx->bbox.X2 - ctx->bbox.X1;
+	ctx->pcb->hidlib.dwg.Y2 = ctx->bbox.Y2 - ctx->bbox.Y1;
 
 	if (!ctx->has_pcb_boundary) {
 		ctx->bbox.X1 = ctx->bbox.Y1 = ctx->bbox.X2 = ctx->bbox.Y2 = 0;
@@ -1600,7 +1600,7 @@
 
 		if (mirror_first) {
 			if (need_mirror)
-				pcb_subc_change_side(nsc, crd[1] * 2 - PCB->hidlib.size_y);
+				pcb_subc_change_side(nsc, crd[1] * 2 - PCB->hidlib.dwg.Y2);
 			if (rot != 0.0)
 				pcb_subc_rotate(nsc, crd[0], crd[1], cos(rot / RND_RAD_TO_DEG), sin(rot / RND_RAD_TO_DEG), rot);
 		}
@@ -1608,7 +1608,7 @@
 			if (rot != 0.0)
 				pcb_subc_rotate(nsc, crd[0], crd[1], cos(rot / RND_RAD_TO_DEG), sin(rot / RND_RAD_TO_DEG), rot);
 			if (need_mirror)
-				pcb_subc_change_side(nsc, crd[1] * 2 - PCB->hidlib.size_y);
+				pcb_subc_change_side(nsc, crd[1] * 2 - PCB->hidlib.dwg.Y2);
 		}
 	}
 
Index: trunk/src_plugins/io_dsn/ses.c
===================================================================
--- trunk/src_plugins/io_dsn/ses.c	(revision 36979)
+++ trunk/src_plugins/io_dsn/ses.c	(revision 36980)
@@ -133,8 +133,8 @@
 			return;
 		(*nlines)++;
 		if (pn > 0) {
-			/*pcb_line_t *line = */pcb_line_new_merge(layer, lx, PCB->hidlib.size_y - ly,
-				x, PCB->hidlib.size_y - y, thick, clear, pcb_flag_make(PCB_FLAG_AUTO | PCB_FLAG_CLEARLINE));
+			/*pcb_line_t *line = */pcb_line_new_merge(layer, lx, PCB->hidlib.dwg.Y2 - ly,
+				x, PCB->hidlib.dwg.Y2 - y, thick, clear, pcb_flag_make(PCB_FLAG_AUTO | PCB_FLAG_CLEARLINE));
 /*				pcb_poly_clear_from_poly(PCB->Data, PCB_OBJ_LINE, layer, line);*/
 /*				rnd_printf("LINE: %$mm %$mm .. %$mm %$mm\n", lx, ly, x, y);*/
 		}
@@ -199,9 +199,9 @@
 	}
 
 	{
-		pcb_pstk_t *ps = pcb_pstk_new(PCB->Data, -1, l1, x, PCB->hidlib.size_y - y, clear, pcb_flag_make(PCB_FLAG_CLEARLINE | PCB_FLAG_AUTO));
+		pcb_pstk_t *ps = pcb_pstk_new(PCB->Data, -1, l1, x, PCB->hidlib.dwg.Y2 - y, clear, pcb_flag_make(PCB_FLAG_CLEARLINE | PCB_FLAG_AUTO));
 		if (ps == NULL)
-			rnd_message(RND_MSG_ERROR, "import_ses: failed to create via at %$mm;%$mm with prototype %ld\n", x, PCB->hidlib.size_y - y, l1);
+			rnd_message(RND_MSG_ERROR, "import_ses: failed to create via at %$mm;%$mm with prototype %ld\n", x, PCB->hidlib.dwg.Y2 - y, l1);
 	}
 }
 
Index: trunk/src_plugins/io_dsn/write.c
===================================================================
--- trunk/src_plugins/io_dsn/write.c	(revision 36979)
+++ trunk/src_plugins/io_dsn/write.c	(revision 36980)
@@ -94,7 +94,7 @@
 /* Board coords */
 #define COORD(c)  (c)
 #define COORDX(x) (x)
-#define COORDY(y) (PCB->hidlib.size_y - (y))
+#define COORDY(y) (PCB->hidlib.dwg.Y2 - (y))
 
 /* local coords (subc or padstack context) */
 #define LCOORD(c)  (c)
@@ -141,7 +141,7 @@
 {
 	pcb_poly_t *bp;
 
-	rnd_fprintf(wctx->f, "    (boundary (rect pcb %[4] %[4] %[4] %[4]))\n", 0, 0, PCB->hidlib.size_x, PCB->hidlib.size_y);
+	rnd_fprintf(wctx->f, "    (boundary (rect pcb %[4] %[4] %[4] %[4]))\n", PCB->hidlib.dwg.X1, PCB->hidlib.dwg.Y1, PCB->hidlib.dwg.X2, PCB->hidlib.dwg.Y2);
 
 	bp = pcb_topoly_1st_outline(wctx->pcb, PCB_TOPOLY_KEEP_ORIG | PCB_TOPOLY_FLOATING);
 	if (bp != NULL) {
Index: trunk/src_plugins/io_eagle/read.c
===================================================================
--- trunk/src_plugins/io_eagle/read.c	(revision 36979)
+++ trunk/src_plugins/io_eagle/read.c	(revision 36980)
@@ -554,10 +554,10 @@
 
 static void size_bump(read_state_t *st, rnd_coord_t x, rnd_coord_t y)
 {
-	if (x > st->pcb->hidlib.size_x)
-		st->pcb->hidlib.size_x = x;
-	if (y > st->pcb->hidlib.size_y)
-		st->pcb->hidlib.size_y = y;
+	if (x > st->pcb->hidlib.dwg.X2)
+		st->pcb->hidlib.dwg.X2 = x;
+	if (y > st->pcb->hidlib.dwg.Y2)
+		st->pcb->hidlib.dwg.Y2 = y;
 }
 
 /* Convert eagle Rxxx to degrees. Binary n*1024 string converted to Rxxx in eagle_bin.c */
@@ -1697,7 +1697,7 @@
 				ang = 0;
 
 			if (back)
-				pcb_subc_change_side(new_subc, 2 * y - st->pcb->hidlib.size_y);
+				pcb_subc_change_side(new_subc, 2 * y - st->pcb->hidlib.dwg.Y2);
 
 			size_bump(st, new_subc->BoundingBox.X2, new_subc->BoundingBox.Y2);
 		}
@@ -2142,7 +2142,7 @@
 		pcb_subc_t *subc = st->fp_parent_data->subc.lst.first;
 		if (subc != NULL) {
 			pcb_undo_freeze_add();
-			pcb_data_mirror(st->fp_data, -PCB->hidlib.size_y, PCB_TXM_COORD | PCB_TXM_ROT, 0, 0);
+			pcb_data_mirror(st->fp_data, -PCB->hidlib.dwg.Y2, PCB_TXM_COORD | PCB_TXM_ROT, 0, 0);
 			pcb_undo_unfreeze_add();
 			pcb_subc_create_aux(subc, 0, 0, 0, 0);
 		}
Index: trunk/src_plugins/io_hyp/parser.c
===================================================================
--- trunk/src_plugins/io_hyp/parser.c	(revision 36979)
+++ trunk/src_plugins/io_hyp/parser.c	(revision 36980)
@@ -650,12 +650,12 @@
 		}
 	}
 
-	width = max(PCB->hidlib.size_x, x_max - x_min + slack);
-	height = max(PCB->hidlib.size_y, y_max - y_min + slack);
+	width = max(rnd_dwg_get_size_x(&PCB->hidlib), x_max - x_min + slack);
+	height = max(rnd_dwg_get_size_y(&PCB->hidlib), y_max - y_min + slack);
 
 	/* resize if board too small */
-	if ((width > PCB->hidlib.size_x) || (height > PCB->hidlib.size_y))
-		pcb_board_resize(width, height, 0);
+	if ((width > PCB->hidlib.dwg.X2) || (height > PCB->hidlib.dwg.Y2))
+		pcb_board_resize(0, 0, width, height, 0);
 
 	return;
 
Index: trunk/src_plugins/io_hyp/write.c
===================================================================
--- trunk/src_plugins/io_hyp/write.c	(revision 36979)
+++ trunk/src_plugins/io_hyp/write.c	(revision 36980)
@@ -59,7 +59,7 @@
 /* pcb-rnd y-axis points down; hyperlynx y-axis points up */
 static rnd_coord_t flip(rnd_coord_t y)
 {
-	return (PCB->hidlib.size_y - y);
+	return (PCB->hidlib.dwg.Y2 - y);
 }
 
 static void hyp_grp_init(hyp_wr_t *wr)
@@ -371,10 +371,10 @@
 	if (!has_outline) {
 		/* implicit outline */
 		fprintf(wr->f, "* implicit outline derived from board width and height\n");
-		write_pr_line(wr, 0, 0, PCB->hidlib.size_x, 0);
-		write_pr_line(wr, 0, 0, 0, PCB->hidlib.size_y);
-		write_pr_line(wr, PCB->hidlib.size_x, 0, PCB->hidlib.size_x, PCB->hidlib.size_y);
-		write_pr_line(wr, 0, PCB->hidlib.size_y, PCB->hidlib.size_x, PCB->hidlib.size_y);
+		write_pr_line(wr, PCB->hidlib.dwg.X1, PCB->hidlib.dwg.Y1, PCB->hidlib.dwg.X2, PCB->hidlib.dwg.Y1);
+		write_pr_line(wr, PCB->hidlib.dwg.X1, PCB->hidlib.dwg.Y1, PCB->hidlib.dwg.X1, PCB->hidlib.dwg.Y2);
+		write_pr_line(wr, PCB->hidlib.dwg.X2, PCB->hidlib.dwg.Y1, PCB->hidlib.dwg.X2, PCB->hidlib.dwg.Y2);
+		write_pr_line(wr, PCB->hidlib.dwg.X1, PCB->hidlib.dwg.Y2, PCB->hidlib.dwg.X2, PCB->hidlib.dwg.Y2);
 	}
 	else { /* explicit outline */
 		for(i = 0, g = PCB->LayerGroups.grp; i < PCB->LayerGroups.len; i++,g++) {
Index: trunk/src_plugins/io_kicad/read.c
===================================================================
--- trunk/src_plugins/io_kicad/read.c	(revision 36979)
+++ trunk/src_plugins/io_kicad/read.c	(revision 36980)
@@ -574,8 +574,8 @@
 	int n;
 	for(n = 0; n < DIM_max; n++) {
 		if (st->dim_valid[n]) {
-			st->pcb->hidlib.size_x = st->width[n];
-			st->pcb->hidlib.size_y = st->height[n];
+			st->pcb->hidlib.dwg.X2 = st->width[n];
+			st->pcb->hidlib.dwg.Y2 = st->height[n];
 			return 0;
 		}
 	}
Index: trunk/src_plugins/io_kicad/write.c
===================================================================
--- trunk/src_plugins/io_kicad/write.c	(revision 36979)
+++ trunk/src_plugins/io_kicad/write.c	(revision 36980)
@@ -924,22 +924,22 @@
 
 TODO(": rewrite this: rather have a table and a loop that hardwired calculations in code")
 	/* we sort out the needed kicad sheet size here, using A4, A3, A2, A1 or A0 size as needed */
-	if (RND_COORD_TO_MIL(PCB->hidlib.size_x) > A4WidthMil || RND_COORD_TO_MIL(PCB->hidlib.size_y) > A4HeightMil) {
+	if (RND_COORD_TO_MIL(PCB->hidlib.dwg.X2) > A4WidthMil || RND_COORD_TO_MIL(PCB->hidlib.dwg.Y2) > A4HeightMil) {
 		sheetHeight = A4WidthMil; /* 11.7" */
 		sheetWidth = 2 * A4HeightMil; /* 16.5" */
 		paperSize = 3; /* this is A3 size */
 	}
-	if (RND_COORD_TO_MIL(PCB->hidlib.size_x) > sheetWidth || RND_COORD_TO_MIL(PCB->hidlib.size_y) > sheetHeight) {
+	if (RND_COORD_TO_MIL(PCB->hidlib.dwg.X2) > sheetWidth || RND_COORD_TO_MIL(PCB->hidlib.dwg.Y2) > sheetHeight) {
 		sheetHeight = 2 * A4HeightMil; /* 16.5" */
 		sheetWidth = 2 * A4WidthMil; /* 23.4" */
 		paperSize = 2; /* this is A2 size */
 	}
-	if (RND_COORD_TO_MIL(PCB->hidlib.size_x) > sheetWidth || RND_COORD_TO_MIL(PCB->hidlib.size_y) > sheetHeight) {
+	if (RND_COORD_TO_MIL(PCB->hidlib.dwg.X2) > sheetWidth || RND_COORD_TO_MIL(PCB->hidlib.dwg.Y2) > sheetHeight) {
 		sheetHeight = 2 * A4WidthMil; /* 23.4" */
 		sheetWidth = 4 * A4HeightMil; /* 33.1" */
 		paperSize = 1; /* this is A1 size */
 	}
-	if (RND_COORD_TO_MIL(PCB->hidlib.size_x) > sheetWidth || RND_COORD_TO_MIL(PCB->hidlib.size_y) > sheetHeight) {
+	if (RND_COORD_TO_MIL(PCB->hidlib.dwg.X2) > sheetWidth || RND_COORD_TO_MIL(PCB->hidlib.dwg.Y2) > sheetHeight) {
 		sheetHeight = 4 * A4HeightMil; /* 33.1" */
 		sheetWidth = 4 * A4WidthMil; /* 46.8"  */
 		paperSize = 0; /* this is A0 size; where would you get it made ?!?! */
@@ -951,20 +951,20 @@
 		rnd_coord_t LayoutYOffset;
 
 		/* we now sort out the offsets for centring the layout in the chosen sheet size here */
-		if (sheetWidth > RND_COORD_TO_MIL(PCB->hidlib.size_x)) { /* usually A4, bigger if needed */
+		if (sheetWidth > RND_COORD_TO_MIL(PCB->hidlib.dwg.X2)) { /* usually A4, bigger if needed */
 			/* fprintf(ctx->f, "%d ", sheetWidth);  legacy kicad: elements decimils, sheet size mils */
-			LayoutXOffset = RND_MIL_TO_COORD(sheetWidth) / 2 - PCB->hidlib.size_x / 2;
+			LayoutXOffset = RND_MIL_TO_COORD(sheetWidth) / 2 - PCB->hidlib.dwg.X2 / 2;
 		}
 		else { /* the layout is bigger than A0; most unlikely, but... */
-			/* rnd_fprintf(ctx->f, "%.0ml ", PCB->hidlib.size_x); */
+			/* rnd_fprintf(ctx->f, "%.0ml ", PCB->hidlib.dwg.X2); */
 			LayoutXOffset = 0;
 		}
-		if (sheetHeight > RND_COORD_TO_MIL(PCB->hidlib.size_y)) {
+		if (sheetHeight > RND_COORD_TO_MIL(PCB->hidlib.dwg.Y2)) {
 			/* fprintf(ctx->f, "%d", sheetHeight); */
-			LayoutYOffset = RND_MIL_TO_COORD(sheetHeight) / 2 - PCB->hidlib.size_y / 2;
+			LayoutYOffset = RND_MIL_TO_COORD(sheetHeight) / 2 - PCB->hidlib.dwg.Y2 / 2;
 		}
 		else { /* the layout is bigger than A0; most unlikely, but... */
-			/* rnd_fprintf(ctx->f, "%.0ml", PCB->hidlib.size_y); */
+			/* rnd_fprintf(ctx->f, "%.0ml", PCB->hidlib.dwg.Y2); */
 			LayoutYOffset = 0;
 	}
 
@@ -980,21 +980,21 @@
 	fprintf(ctx->f, "%*s", ind, "");
 	rnd_fprintf(ctx->f, "(gr_line (start %.3mm %.3mm) (end %.3mm %.3mm) (layer %s) (width %.3mm))\n",
 		ctx->ox, ctx->oy,
-		ctx->pcb->hidlib.size_x + ctx->ox, ctx->oy,
+		ctx->pcb->hidlib.dwg.X2 + ctx->ox, ctx->oy,
 		lynam, thick);
 	fprintf(ctx->f, "%*s", ind, "");
 	rnd_fprintf(ctx->f, "(gr_line (start %.3mm %.3mm) (end %.3mm %.3mm) (layer %s) (width %.3mm))\n",
-		ctx->pcb->hidlib.size_x + ctx->ox, ctx->oy,
-		ctx->pcb->hidlib.size_x + ctx->ox, ctx->pcb->hidlib.size_y + ctx->oy,
+		ctx->pcb->hidlib.dwg.X2 + ctx->ox, ctx->oy,
+		ctx->pcb->hidlib.dwg.X2 + ctx->ox, ctx->pcb->hidlib.dwg.Y2 + ctx->oy,
 		lynam, thick);
 	fprintf(ctx->f, "%*s", ind, "");
 	rnd_fprintf(ctx->f, "(gr_line (start %.3mm %.3mm) (end %.3mm %.3mm) (layer %s) (width %.3mm))\n",
-		ctx->pcb->hidlib.size_x + ctx->ox, ctx->pcb->hidlib.size_y + ctx->oy,
-		ctx->ox, ctx->pcb->hidlib.size_y + ctx->oy,
+		ctx->pcb->hidlib.dwg.X2 + ctx->ox, ctx->pcb->hidlib.dwg.Y2 + ctx->oy,
+		ctx->ox, ctx->pcb->hidlib.dwg.Y2 + ctx->oy,
 		lynam, thick);
 	fprintf(ctx->f, "%*s", ind, "");
 	rnd_fprintf(ctx->f, "(gr_line (start %.3mm %.3mm) (end %.3mm %.3mm) (layer %s) (width %.3mm))\n",
-		ctx->ox, ctx->pcb->hidlib.size_y + ctx->oy,
+		ctx->ox, ctx->pcb->hidlib.dwg.Y2 + ctx->oy,
 		ctx->ox, ctx->oy,
 		lynam, thick);
 }
Index: trunk/src_plugins/io_kicad_legacy/write.c
===================================================================
--- trunk/src_plugins/io_kicad_legacy/write.c	(revision 36979)
+++ trunk/src_plugins/io_kicad_legacy/write.c	(revision 36980)
@@ -761,22 +761,22 @@
 
 TODO(": se this from io_kicad, do not duplicate the code here")
 	/* we sort out the needed kicad sheet size here, using A4, A3, A2, A1 or A0 size as needed */
-	if (RND_COORD_TO_MIL(PCB->hidlib.size_x) > A4WidthMil || RND_COORD_TO_MIL(PCB->hidlib.size_y) > A4HeightMil) {
+	if (RND_COORD_TO_MIL(PCB->hidlib.dwg.X2) > A4WidthMil || RND_COORD_TO_MIL(PCB->hidlib.dwg.Y2) > A4HeightMil) {
 		sheetHeight = A4WidthMil; /* 11.7" */
 		sheetWidth = 2 * A4HeightMil; /* 16.5" */
 		paperSize = 3; /* this is A3 size */
 	}
-	if (RND_COORD_TO_MIL(PCB->hidlib.size_x) > sheetWidth || RND_COORD_TO_MIL(PCB->hidlib.size_y) > sheetHeight) {
+	if (RND_COORD_TO_MIL(PCB->hidlib.dwg.X2) > sheetWidth || RND_COORD_TO_MIL(PCB->hidlib.dwg.Y2) > sheetHeight) {
 		sheetHeight = 2 * A4HeightMil; /* 16.5" */
 		sheetWidth = 2 * A4WidthMil; /* 23.4" */
 		paperSize = 2; /* this is A2 size */
 	}
-	if (RND_COORD_TO_MIL(PCB->hidlib.size_x) > sheetWidth || RND_COORD_TO_MIL(PCB->hidlib.size_y) > sheetHeight) {
+	if (RND_COORD_TO_MIL(PCB->hidlib.dwg.X2) > sheetWidth || RND_COORD_TO_MIL(PCB->hidlib.dwg.Y2) > sheetHeight) {
 		sheetHeight = 2 * A4WidthMil; /* 23.4" */
 		sheetWidth = 4 * A4HeightMil; /* 33.1" */
 		paperSize = 1; /* this is A1 size */
 	}
-	if (RND_COORD_TO_MIL(PCB->hidlib.size_x) > sheetWidth || RND_COORD_TO_MIL(PCB->hidlib.size_y) > sheetHeight) {
+	if (RND_COORD_TO_MIL(PCB->hidlib.dwg.X2) > sheetWidth || RND_COORD_TO_MIL(PCB->hidlib.dwg.Y2) > sheetHeight) {
 		sheetHeight = 4 * A4HeightMil; /* 33.1" */
 		sheetWidth = 4 * A4WidthMil; /* 46.8"  */
 		paperSize = 0; /* this is A0 size; where would you get it made ?!?! */
@@ -784,20 +784,20 @@
 
 	fprintf(FP, "Sheet A%d ", paperSize);
 	/* we now sort out the offsets for centring the layout in the chosen sheet size here */
-	if (sheetWidth > RND_COORD_TO_MIL(PCB->hidlib.size_x)) { /* usually A4, bigger if needed */
+	if (sheetWidth > RND_COORD_TO_MIL(PCB->hidlib.dwg.X2)) { /* usually A4, bigger if needed */
 		fprintf(FP, "%d ", sheetWidth); /* legacy kicad: elements decimils, sheet size mils */
-		LayoutXOffset = RND_MIL_TO_COORD(sheetWidth) / 2 - PCB->hidlib.size_x / 2;
+		LayoutXOffset = RND_MIL_TO_COORD(sheetWidth) / 2 - PCB->hidlib.dwg.X2 / 2;
 	}
 	else { /* the layout is bigger than A0; most unlikely, but... */
-		rnd_fprintf(FP, "%.0ml ", PCB->hidlib.size_x);
+		rnd_fprintf(FP, "%.0ml ", PCB->hidlib.dwg.X2);
 		LayoutXOffset = 0;
 	}
-	if (sheetHeight > RND_COORD_TO_MIL(PCB->hidlib.size_y)) {
+	if (sheetHeight > RND_COORD_TO_MIL(PCB->hidlib.dwg.Y2)) {
 		fprintf(FP, "%d", sheetHeight);
-		LayoutYOffset = RND_MIL_TO_COORD(sheetHeight) / 2 - PCB->hidlib.size_y / 2;
+		LayoutYOffset = RND_MIL_TO_COORD(sheetHeight) / 2 - PCB->hidlib.dwg.Y2 / 2;
 	}
 	else { /* the layout is bigger than A0; most unlikely, but... */
-		rnd_fprintf(FP, "%.0ml", PCB->hidlib.size_y);
+		rnd_fprintf(FP, "%.0ml", PCB->hidlib.dwg.Y2);
 		LayoutYOffset = 0;
 	}
 	fputs("\n", FP);
@@ -908,19 +908,19 @@
 	}
 	else { /* no outline layer per se, export the board margins instead  - obviously some scope to reduce redundant code... */
 		fputs("$DRAWSEGMENT\n", FP);
-		rnd_fprintf(FP, "Po 0 %.0mk %.0mk %.0mk %.0mk %.0mk\n", PCB->hidlib.size_x / 2 - LayoutXOffset, PCB->hidlib.size_y / 2 - LayoutYOffset, PCB->hidlib.size_x / 2 + LayoutXOffset, PCB->hidlib.size_y / 2 - LayoutYOffset, outlineThickness);
+		rnd_fprintf(FP, "Po 0 %.0mk %.0mk %.0mk %.0mk %.0mk\n", PCB->hidlib.dwg.X2 / 2 - LayoutXOffset, PCB->hidlib.dwg.Y2 / 2 - LayoutYOffset, PCB->hidlib.dwg.X2 / 2 + LayoutXOffset, PCB->hidlib.dwg.Y2 / 2 - LayoutYOffset, outlineThickness);
 		rnd_fprintf(FP, "De %d 0 0 0 0\n", currentKicadLayer);
 		fputs("$EndDRAWSEGMENT\n", FP);
 		fputs("$DRAWSEGMENT\n", FP);
-		rnd_fprintf(FP, "Po 0 %.0mk %.0mk %.0mk %.0mk %.0mk\n", PCB->hidlib.size_x / 2 + LayoutXOffset, PCB->hidlib.size_y / 2 - LayoutYOffset, PCB->hidlib.size_x / 2 + LayoutXOffset, PCB->hidlib.size_y / 2 + LayoutYOffset, outlineThickness);
+		rnd_fprintf(FP, "Po 0 %.0mk %.0mk %.0mk %.0mk %.0mk\n", PCB->hidlib.dwg.X2 / 2 + LayoutXOffset, PCB->hidlib.dwg.Y2 / 2 - LayoutYOffset, PCB->hidlib.dwg.X2 / 2 + LayoutXOffset, PCB->hidlib.dwg.Y2 / 2 + LayoutYOffset, outlineThickness);
 		rnd_fprintf(FP, "De %d 0 0 0 0\n", currentKicadLayer);
 		fputs("$EndDRAWSEGMENT\n", FP);
 		fputs("$DRAWSEGMENT\n", FP);
-		rnd_fprintf(FP, "Po 0 %.0mk %.0mk %.0mk %.0mk %.0mk\n", PCB->hidlib.size_x / 2 + LayoutXOffset, PCB->hidlib.size_y / 2 + LayoutYOffset, PCB->hidlib.size_x / 2 - LayoutXOffset, PCB->hidlib.size_y / 2 + LayoutYOffset, outlineThickness);
+		rnd_fprintf(FP, "Po 0 %.0mk %.0mk %.0mk %.0mk %.0mk\n", PCB->hidlib.dwg.X2 / 2 + LayoutXOffset, PCB->hidlib.dwg.Y2 / 2 + LayoutYOffset, PCB->hidlib.dwg.X2 / 2 - LayoutXOffset, PCB->hidlib.dwg.Y2 / 2 + LayoutYOffset, outlineThickness);
 		rnd_fprintf(FP, "De %d 0 0 0 0\n", currentKicadLayer);
 		fputs("$EndDRAWSEGMENT\n", FP);
 		fputs("$DRAWSEGMENT\n", FP);
-		rnd_fprintf(FP, "Po 0 %.0mk %.0mk %.0mk %.0mk %.0mk\n", PCB->hidlib.size_x / 2 - LayoutXOffset, PCB->hidlib.size_y / 2 + LayoutYOffset, PCB->hidlib.size_x / 2 - LayoutXOffset, PCB->hidlib.size_y / 2 - LayoutYOffset, outlineThickness);
+		rnd_fprintf(FP, "Po 0 %.0mk %.0mk %.0mk %.0mk %.0mk\n", PCB->hidlib.dwg.X2 / 2 - LayoutXOffset, PCB->hidlib.dwg.Y2 / 2 + LayoutYOffset, PCB->hidlib.dwg.X2 / 2 - LayoutXOffset, PCB->hidlib.dwg.Y2 / 2 - LayoutYOffset, outlineThickness);
 		rnd_fprintf(FP, "De %d 0 0 0 0\n", currentKicadLayer);
 		fputs("$EndDRAWSEGMENT\n", FP);
 	}
Index: trunk/src_plugins/io_lihata/read.c
===================================================================
--- trunk/src_plugins/io_lihata/read.c	(revision 36979)
+++ trunk/src_plugins/io_lihata/read.c	(revision 36980)
@@ -454,8 +454,8 @@
 
 	grp = lht_dom_hash_get(nd, "size");
 	if ((grp != NULL) && (grp->type == LHT_HASH)) {
-		err |= parse_coord(&pcb->hidlib.size_x, hash_get(grp, "x", 0));
-		err |= parse_coord(&pcb->hidlib.size_y, hash_get(grp, "y", 0));
+		err |= parse_coord(&pcb->hidlib.dwg.X2, hash_get(grp, "x", 0));
+		err |= parse_coord(&pcb->hidlib.dwg.Y2, hash_get(grp, "y", 0));
 		err |= parse_coord_conf(rctx, "design/poly_isle_area", hash_get(grp, "isle_area_nm2", 1));
 		err |= parse_double(&pcb->ThermScale, hash_get(grp, "thermal_scale", 1));
 		if (pcb->ThermScale < 0.01) {
Index: trunk/src_plugins/io_lihata/write.c
===================================================================
--- trunk/src_plugins/io_lihata/write.c	(revision 36979)
+++ trunk/src_plugins/io_lihata/write.c	(revision 36980)
@@ -174,8 +174,11 @@
 
 	grp = lht_dom_node_alloc(LHT_HASH, "size");
 	lht_dom_hash_put(meta, grp);
-	lht_dom_hash_put(grp, build_textf("x", CFMT, pcb->hidlib.size_x));
-	lht_dom_hash_put(grp, build_textf("y", CFMT, pcb->hidlib.size_y));
+	lht_dom_hash_put(grp, build_textf("x", CFMT, pcb->hidlib.dwg.X2));
+	lht_dom_hash_put(grp, build_textf("y", CFMT, pcb->hidlib.dwg.Y2));
+	if ((pcb->hidlib.dwg.X1 != 0) || (pcb->hidlib.dwg.Y1 != 0))
+		pcb_io_incompat_save(NULL, NULL, "board", "drawing are bbox with non-zero origin (X1 or Y1)\n", "Run autocrop()");
+
 	if (wrver < 5) {
 		lht_dom_hash_put(grp, build_textf("isle_area_nm2", "%f", conf_core.design.poly_isle_area));
 	}
Index: trunk/src_plugins/io_mentor_cell/read.c
===================================================================
--- trunk/src_plugins/io_mentor_cell/read.c	(revision 36979)
+++ trunk/src_plugins/io_mentor_cell/read.c	(revision 36980)
@@ -1217,8 +1217,8 @@
 		rnd_box_t bb;
 		pcb_data_normalize(ctx->pcb->Data);
 		pcb_data_bbox(&bb, ctx->pcb->Data, 0);
-		ctx->pcb->hidlib.size_x = bb.X2;
-		ctx->pcb->hidlib.size_y = bb.Y2;
+		ctx->pcb->hidlib.dwg.X2 = bb.X2;
+		ctx->pcb->hidlib.dwg.Y2 = bb.Y2;
 	}
 
 	return 0;
Index: trunk/src_plugins/io_pads/delay_create.c
===================================================================
--- trunk/src_plugins/io_pads/delay_create.c	(revision 36979)
+++ trunk/src_plugins/io_pads/delay_create.c	(revision 36980)
@@ -686,7 +686,7 @@
 		rnd_coord_t cx = 0, cy = 0;
 		pcb_subc_get_origin(subc, &cx, &cy);
 		cy += obj->val.subc_from_lib.y;
-		pcb_subc_change_side(nsc, (pcb->hidlib.size_y - 2*cy));
+		pcb_subc_change_side(nsc, (pcb->hidlib.dwg.Y2 - 2*cy));
 		rot = 180-rot;
 	}
 
@@ -833,7 +833,7 @@
 {
 	pcb_dlcr_create_layers(pcb, dlcr);
 	pcb_dlcr_create_pstk_protos(pcb, dlcr, pcb->Data, &dlcr->pstks);
-	pcb->hidlib.size_x = dlcr->board_bbox.X2;
-	pcb->hidlib.size_y = dlcr->board_bbox.Y2;
+	pcb->hidlib.dwg.X2 = dlcr->board_bbox.X2;
+	pcb->hidlib.dwg.Y2 = dlcr->board_bbox.Y2;
 	pcb_dlcr_create_drawings(pcb, dlcr);
 }
Index: trunk/src_plugins/io_pads/write.c
===================================================================
--- trunk/src_plugins/io_pads/write.c	(revision 36979)
+++ trunk/src_plugins/io_pads/write.c	(revision 36980)
@@ -72,7 +72,7 @@
 
 #define CRD(c)   (c)
 #define CRDX(c)  CRD(c)
-#define CRDY(c)  CRD((wctx->writing_partdecal ? 0 : wctx->pcb->hidlib.size_y) - (c))
+#define CRDY(c)  CRD((wctx->writing_partdecal ? 0 : wctx->pcb->hidlib.dwg.Y2) - (c))
 #define ROT(r)   (r)
 
 #include "write_layer.c"
@@ -108,7 +108,7 @@
 	rnd_fprintf(wctx->f, "DOTGRID      %[4]  %[4]      Space between graphic dots\r\n", CRD(rnd_conf.editor.grid), CRD(rnd_conf.editor.grid));
 	fprintf(wctx->f, "SCALE        10.000              Scale of window expansion\r\n");
 	rnd_fprintf(wctx->f, "ORIGIN       %[4]  %[4]      User defined origin location\r\n", CRD(wctx->pcb->hidlib.grid_ox), CRD(wctx->pcb->hidlib.grid_oy));
-	rnd_fprintf(wctx->f, "WINDOWCENTER %[4] %[4]     Point defining the center of the window\r\n", CRD(wctx->pcb->hidlib.size_x/2.0), CRD(wctx->pcb->hidlib.size_y/2.0));
+	rnd_fprintf(wctx->f, "WINDOWCENTER %[4] %[4]     Point defining the center of the window\r\n", CRD((wctx->pcb->hidlib.dwg.X1+wctx->pcb->hidlib.dwg.X2)/2.0), CRD((wctx->pcb->hidlib.dwg.Y1+wctx->pcb->hidlib.dwg.Y2)/2.0));
 	fprintf(wctx->f, "BACKUPTIME       20              Number of minutes between database backups\r\n");
 	fprintf(wctx->f, "REAL WIDTH        2              Widths greater then this are displayed real size\r\n");
 	fprintf(wctx->f, "ALLSIGONOFF       1              All signal nets displayed on/off\r\n");
Index: trunk/src_plugins/io_pcb/file.c
===================================================================
--- trunk/src_plugins/io_pcb/file.c	(revision 36979)
+++ trunk/src_plugins/io_pcb/file.c	(revision 36980)
@@ -293,7 +293,7 @@
 
 	fputs("\nPCB[", FP);
 	pcb_print_quoted_string(FP, (char *) RND_EMPTY(PCB->hidlib.name));
-	rnd_fprintf(FP, " %[0] %[0]]\n\n", PCB->hidlib.size_x, PCB->hidlib.size_y);
+	rnd_fprintf(FP, " %[0] %[0]]\n\n", PCB->hidlib.dwg.X2, PCB->hidlib.dwg.Y2);
 	rnd_fprintf(FP, "Grid[%[0] %[0] %[0] %d]\n", PCB->hidlib.grid, PCB->hidlib.grid_ox, PCB->hidlib.grid_oy, rnd_conf.editor.draw_grid);
 	rnd_fprintf(FP, "Cursor[%[0] %[0] 1000]\n", pcb_crosshair.X, pcb_crosshair.Y);
 	/* PolyArea should be output in square cmils, no suffix */
@@ -835,8 +835,8 @@
 	pcb_data_bbox(&dbb, yyPCB->Data, rnd_false);
 	pcb_data_normalize_(yyPCB->Data, &dbb);
 	PCB = pcb_save;
-	yyPCB->hidlib.size_x = dbb.X2*2;
-	yyPCB->hidlib.size_y = dbb.Y2*2;
+	yyPCB->hidlib.dwg.X2 = dbb.X2*2;
+	yyPCB->hidlib.dwg.Y2 = dbb.Y2*2;
 	yyPCB->is_footprint = 1;
 
 	/* opening a footprint: we don't have a layer stack; make sure top and bottom copper exist */
Index: trunk/src_plugins/io_pcb/parse_y.c
===================================================================
--- trunk/src_plugins/io_pcb/parse_y.c	(revision 36979)
+++ trunk/src_plugins/io_pcb/parse_y.c	(revision 36980)
@@ -1981,8 +1981,8 @@
 #line 318 "parse_y.y" /* yacc.c:1652  */
     {
 				yyPCB->hidlib.name = (yyvsp[-1].string);
-				yyPCB->hidlib.size_x = RND_MAX_COORD;
-				yyPCB->hidlib.size_y = RND_MAX_COORD;
+				yyPCB->hidlib.dwg.X2 = RND_MAX_COORD;
+				yyPCB->hidlib.dwg.Y2 = RND_MAX_COORD;
 				old_fmt = 1;
 			}
 #line 1989 "parse_y.c" /* yacc.c:1652  */
@@ -1992,8 +1992,8 @@
 #line 325 "parse_y.y" /* yacc.c:1652  */
     {
 				yyPCB->hidlib.name = (yyvsp[-3].string);
-				yyPCB->hidlib.size_x = OU ((yyvsp[-2].measure));
-				yyPCB->hidlib.size_y = OU ((yyvsp[-1].measure));
+				yyPCB->hidlib.dwg.X2 = OU ((yyvsp[-2].measure));
+				yyPCB->hidlib.dwg.Y2 = OU ((yyvsp[-1].measure));
 				old_fmt = 1;
 			}
 #line 2000 "parse_y.c" /* yacc.c:1652  */
@@ -2003,8 +2003,8 @@
 #line 332 "parse_y.y" /* yacc.c:1652  */
     {
 				yyPCB->hidlib.name = (yyvsp[-3].string);
-				yyPCB->hidlib.size_x = NU ((yyvsp[-2].measure));
-				yyPCB->hidlib.size_y = NU ((yyvsp[-1].measure));
+				yyPCB->hidlib.dwg.X2 = NU ((yyvsp[-2].measure));
+				yyPCB->hidlib.dwg.Y2 = NU ((yyvsp[-1].measure));
 				old_fmt = 0;
 			}
 #line 2011 "parse_y.c" /* yacc.c:1652  */
Index: trunk/src_plugins/io_pcb/parse_y.y
===================================================================
--- trunk/src_plugins/io_pcb/parse_y.y	(revision 36979)
+++ trunk/src_plugins/io_pcb/parse_y.y	(revision 36980)
@@ -317,22 +317,22 @@
 		: T_PCB '(' STRING ')'
 			{
 				yyPCB->hidlib.name = $3;
-				yyPCB->hidlib.size_x = RND_MAX_COORD;
-				yyPCB->hidlib.size_y = RND_MAX_COORD;
+				yyPCB->hidlib.dwg.X2 = RND_MAX_COORD;
+				yyPCB->hidlib.dwg.Y2 = RND_MAX_COORD;
 				old_fmt = 1;
 			}
 		| T_PCB '(' STRING measure measure ')'
 			{
 				yyPCB->hidlib.name = $3;
-				yyPCB->hidlib.size_x = OU ($4);
-				yyPCB->hidlib.size_y = OU ($5);
+				yyPCB->hidlib.dwg.X2 = OU ($4);
+				yyPCB->hidlib.dwg.Y2 = OU ($5);
 				old_fmt = 1;
 			}
 		| T_PCB '[' STRING measure measure ']'
 			{
 				yyPCB->hidlib.name = $3;
-				yyPCB->hidlib.size_x = NU ($4);
-				yyPCB->hidlib.size_y = NU ($5);
+				yyPCB->hidlib.dwg.X2 = NU ($4);
+				yyPCB->hidlib.dwg.Y2 = NU ($5);
 				old_fmt = 0;
 			}
 		;
Index: trunk/src_plugins/io_tedax/tboard.c
===================================================================
--- trunk/src_plugins/io_tedax/tboard.c	(revision 36979)
+++ trunk/src_plugins/io_tedax/tboard.c	(revision 36980)
@@ -149,7 +149,7 @@
 	fprintf(f, "\nbegin board v1 ");
 	tedax_fprint_escape(f, pcb->hidlib.name);
 	fputc('\n', f);
-	rnd_fprintf(f, " drawing_area 0 0 %.06mm %.06mm\n", pcb->hidlib.size_x, pcb->hidlib.size_y);
+	rnd_fprintf(f, " drawing_area %.06mm %.06mm %.06mm %.06mm\n", pcb->hidlib.dwg.X1, pcb->hidlib.dwg.Y1, pcb->hidlib.dwg.X2, pcb->hidlib.dwg.Y2);
 	for(n = 0, a = pcb->Attributes.List; n < pcb->Attributes.Number; n++,a++) {
 		rnd_fprintf(f, " attr ");
 		tedax_fprint_escape(f, a->name);
@@ -386,8 +386,10 @@
 			if (!succ) errexit("Invalid y2 coord in drawing_area\n");
 			if ((x1 >= x2) || (y1 >= y2)) errexit("Invalid (unordered, negative box) drawing area\n");
 			if ((x1 < 0) || (y1 < 0)) rnd_message(RND_MSG_WARNING, "drawing_area starts at negative coords; some objects may not display;\nyou may want to run autocrop()\n");
-			PCB->hidlib.size_x = x2 - x1;
-			PCB->hidlib.size_y = y2 - y1;
+			PCB->hidlib.dwg.X1 = /*x1*/ 0;
+			PCB->hidlib.dwg.Y1 = /*y1*/ 0;
+			PCB->hidlib.dwg.X2 = x2;
+			PCB->hidlib.dwg.Y2 = y2;
 		}
 		else if (strcmp(argv[0], "attr") == 0) {
 			reqarg("attr", 3);
Index: trunk/src_plugins/lib_netmap/placement.c
===================================================================
--- trunk/src_plugins/lib_netmap/placement.c	(revision 36979)
+++ trunk/src_plugins/lib_netmap/placement.c	(revision 36980)
@@ -61,7 +61,7 @@
 			}
 			if (tr.on_bottom) {
 				int n;
-				pcb_data_mirror(proto->data, ctx->fix_ymirr ? -ctx->pcb->hidlib.size_y : 0, PCB_TXM_SIDE, 1, 0);
+				pcb_data_mirror(proto->data, ctx->fix_ymirr ? -ctx->pcb->hidlib.dwg.Y2 : 0, PCB_TXM_SIDE, 1, 0);
 				for(n = 0; n < proto->data->LayerN; n++) {
 					pcb_layer_t *ly = proto->data->Layer + n;
 					ly->meta.bound.type = pcb_layer_mirror_type(ly->meta.bound.type);
Index: trunk/src_plugins/lib_polyhelp/topoly.c
===================================================================
--- trunk/src_plugins/lib_polyhelp/topoly.c	(revision 36979)
+++ trunk/src_plugins/lib_polyhelp/topoly.c	(revision 36980)
@@ -357,7 +357,8 @@
 	pcb_layer_t *layer;
 	pcb_any_obj_t *best = NULL;
 	rnd_coord_t x, y;
-	double bestd = (double)pcb->hidlib.size_y*(double)pcb->hidlib.size_y + (double)pcb->hidlib.size_x*(double)pcb->hidlib.size_x;
+	double bw = rnd_dwg_get_size_x(&pcb->hidlib), bh = rnd_dwg_get_size_y(&pcb->hidlib);
+	double bestd = bw*bw + bh*bh;
 
 	for(lid = 0; lid < pcb->Data->LayerN; lid++) {
 		if (!PCB_LAYER_IS_OUTLINE(pcb_layer_flags(PCB, lid), pcb_layer_purpose(PCB, lid, NULL)))
@@ -395,10 +396,10 @@
 
 	if (start == NULL) {
 		poly = pcb_poly_alloc(pcb->Data->Layer);
-		pcb_poly_point_new(poly, 0, 0);
-		pcb_poly_point_new(poly, pcb->hidlib.size_x, 0);
-		pcb_poly_point_new(poly, pcb->hidlib.size_x, pcb->hidlib.size_y);
-		pcb_poly_point_new(poly, 0, pcb->hidlib.size_y);
+		pcb_poly_point_new(poly, pcb->hidlib.dwg.X1, pcb->hidlib.dwg.Y1);
+		pcb_poly_point_new(poly, pcb->hidlib.dwg.X2, pcb->hidlib.dwg.Y1);
+		pcb_poly_point_new(poly, pcb->hidlib.dwg.X2, pcb->hidlib.dwg.Y2);
+		pcb_poly_point_new(poly, pcb->hidlib.dwg.X1, pcb->hidlib.dwg.Y2);
 	}
 	else
 		poly = pcb_topoly_conn_with(pcb, start, how, df);
Index: trunk/src_plugins/millpath/toolpath.c
===================================================================
--- trunk/src_plugins/millpath/toolpath.c	(revision 36979)
+++ trunk/src_plugins/millpath/toolpath.c	(revision 36980)
@@ -257,8 +257,8 @@
 		result->remain = pcb_poly_new_from_rectangle(result->res_remply, otlbb.X1, otlbb.Y1, otlbb.X2, otlbb.Y2, 0, pcb_flag_make(PCB_FLAG_FULLPOLY));
 	}
 	else {
-		result->fill = pcb_poly_new_from_rectangle(result->res_ply, 0, 0, pcb->hidlib.size_x, pcb->hidlib.size_y, 0, pcb_flag_make(PCB_FLAG_FULLPOLY));
-		result->remain = pcb_poly_new_from_rectangle(result->res_remply, 0, 0, pcb->hidlib.size_x, pcb->hidlib.size_y, 0, pcb_flag_make(PCB_FLAG_FULLPOLY));
+		result->fill = pcb_poly_new_from_rectangle(result->res_ply, pcb->hidlib.dwg.X1, pcb->hidlib.dwg.Y1, pcb->hidlib.dwg.X2, pcb->hidlib.dwg.Y2, 0, pcb_flag_make(PCB_FLAG_FULLPOLY));
+		result->remain = pcb_poly_new_from_rectangle(result->res_remply, pcb->hidlib.dwg.X1, pcb->hidlib.dwg.Y1, pcb->hidlib.dwg.X2, pcb->hidlib.dwg.Y2, 0, pcb_flag_make(PCB_FLAG_FULLPOLY));
 	}
 
 	pcb_poly_init_clip(pcb->Data, result->res_ply, result->fill);
Index: trunk/src_plugins/order/order.c
===================================================================
--- trunk/src_plugins/order/order.c	(revision 36979)
+++ trunk/src_plugins/order/order.c	(revision 36980)
@@ -174,7 +174,7 @@
 				autoload_field_crd(octx, f, bb.X2 - bb.X1);
 			}
 			else
-				autoload_field_crd(octx, f, PCB->hidlib.size_x);
+				autoload_field_crd(octx, f, rnd_dwg_get_size_x(&PCB->hidlib));
 			break;
 		case PCB_OAL_HEIGHT:
 			if (has_outline(PCB)) {
@@ -182,7 +182,7 @@
 				autoload_field_crd(octx, f, bb.Y2 - bb.Y1);
 			}
 			else
-				autoload_field_crd(octx, f, PCB->hidlib.size_y);
+				autoload_field_crd(octx, f, rnd_dwg_get_size_y(&PCB->hidlib));
 			break;
 		case PCB_OAL_LAYERS:
 			for(gid = 0, l = 0; gid < PCB->LayerGroups.len; gid++)
Index: trunk/src_plugins/propedit/propsel.c
===================================================================
--- trunk/src_plugins/propedit/propsel.c	(revision 36979)
+++ trunk/src_plugins/propedit/propsel.c	(revision 36980)
@@ -128,8 +128,8 @@
 {
 	map_add_prop(ctx, "p/board/name",   String, pcb->hidlib.name);
 	map_add_prop(ctx, "p/board/filename",   String, pcb->hidlib.filename);
-	map_add_prop(ctx, "p/board/width", rnd_coord_t, pcb->hidlib.size_x);
-	map_add_prop(ctx, "p/board/height", rnd_coord_t, pcb->hidlib.size_y);
+	map_add_prop(ctx, "p/board/width", rnd_coord_t, rnd_dwg_get_size_x(&pcb->hidlib));
+	map_add_prop(ctx, "p/board/height", rnd_coord_t, rnd_dwg_get_size_y(&pcb->hidlib));
 	map_attr(ctx, &pcb->Attributes);
 }
 
@@ -518,9 +518,9 @@
 	return 0;
 }
 
-static int brd_resize(rnd_coord_t w, rnd_coord_t h)
+static int brd_resize(rnd_coord_t x1, rnd_coord_t y1, rnd_coord_t x2, rnd_coord_t y2)
 {
-	pcb_board_resize(w, h, 0);
+	pcb_board_resize(x1, y1, x2, y2, 0);
 	return 1;
 }
 
@@ -547,10 +547,10 @@
 		}
 
 		if (st->c_valid && (strcmp(pn, "width") == 0) &&
-		    brd_resize(st->c, PCB->hidlib.size_y)) DONE;
+		    brd_resize(PCB->hidlib.dwg.X1, PCB->hidlib.dwg.Y1, PCB->hidlib.dwg.X1 + st->c, PCB->hidlib.dwg.Y2)) DONE;
 
 		if (st->c_valid && (strcmp(pn, "height") == 0) &&
-		    brd_resize(PCB->hidlib.size_x,st->c)) DONE;
+		    brd_resize(PCB->hidlib.dwg.X1, PCB->hidlib.dwg.Y1, PCB->hidlib.dwg.X2, PCB->hidlib.dwg.Y1 + st->c)) DONE;
 	}
 }
 
Index: trunk/src_plugins/query/query_l.c
===================================================================
--- trunk/src_plugins/query/query_l.c	(revision 36979)
+++ trunk/src_plugins/query/query_l.c	(revision 36980)
@@ -1448,12 +1448,12 @@
 case 52:
 YY_RULE_SETUP
 #line 105 "query_l.l"
-{ qry_lval.c = PCB->hidlib.size_x; return T_INT; }
+{ qry_lval.c = rnd_dwg_get_size_x(&PCB->hidlib); return T_INT; }
 	YY_BREAK
 case 53:
 YY_RULE_SETUP
 #line 106 "query_l.l"
-{ qry_lval.c = PCB->hidlib.size_y; return T_INT; }
+{ qry_lval.c = rnd_dwg_get_size_y(&PCB->hidlib); return T_INT; }
 	YY_BREAK
 case 54:
 YY_RULE_SETUP
Index: trunk/src_plugins/query/query_l.l
===================================================================
--- trunk/src_plugins/query/query_l.l	(revision 36979)
+++ trunk/src_plugins/query/query_l.l	(revision 36980)
@@ -102,8 +102,8 @@
 "DRCMEASURE"    { qry_lval.n = make_const_obj(yytext, &pcb_qry_drc_ctrl[PCB_QRY_DRC_MEASURE]); return T_CONST; }
 "DRCTEXT"       { qry_lval.n = make_const_obj(yytext, &pcb_qry_drc_ctrl[PCB_QRY_DRC_TEXT]); return T_CONST; }
 
-"$dwg_area_x"   { qry_lval.c = PCB->hidlib.size_x; return T_INT; }
-"$dwg_area_y"   { qry_lval.c = PCB->hidlib.size_y; return T_INT; }
+"$dwg_area_x"   { qry_lval.c = rnd_dwg_get_size_x(&PCB->hidlib); return T_INT; }
+"$dwg_area_y"   { qry_lval.c = rnd_dwg_get_size_y(&PCB->hidlib); return T_INT; }
 
 mm              { qry_lval.u = rnd_get_unit_struct_by_allow(RND_UNIT_ALLOW_MM); return T_UNIT; }
 m               { qry_lval.u = rnd_get_unit_struct_by_allow(RND_UNIT_ALLOW_M); return T_UNIT; }
Index: trunk/src_plugins/report/report.c
===================================================================
--- trunk/src_plugins/report/report.c	(revision 36979)
+++ trunk/src_plugins/report/report.c	(revision 36980)
@@ -805,7 +805,7 @@
 		return 0;
 	}
 	printf("Filename: %s\n", PCB->hidlib.filename);
-	rnd_printf("Size: %ml x %ml mils, %mm x %mm mm\n", PCB->hidlib.size_x, PCB->hidlib.size_y, PCB->hidlib.size_x, PCB->hidlib.size_y);
+	rnd_printf("Size: %ml x %ml mils, %mm x %mm mm\n", rnd_dwg_get_size_x(&PCB->hidlib), rnd_dwg_get_size_y(&PCB->hidlib), rnd_dwg_get_size_x(&PCB->hidlib), rnd_dwg_get_size_y(&PCB->hidlib));
 	for (i = 0; i < PCB_MAX_LAYER; i++) {
 		rnd_layergrp_id_t lg = pcb_layer_get_group(PCB, i);
 		unsigned int gflg = pcb_layergrp_flags(PCB, lg);
Index: trunk/src_plugins/shape/shape.c
===================================================================
--- trunk/src_plugins/shape/shape.c	(revision 36979)
+++ trunk/src_plugins/shape/shape.c	(revision 36980)
@@ -631,7 +631,7 @@
 		return 0;
 	}
 
-	if ((dia < 1) || (dia > (PCB->hidlib.size_x + PCB->hidlib.size_y)/4)) {
+	if ((dia < 1) || (dia > (rnd_dwg_get_size_x(&PCB->hidlib) + rnd_dwg_get_size_y(&PCB->hidlib))/4)) {
 		rnd_message(RND_MSG_ERROR, "circle(): invalid diameter\n");
 		RND_ACT_IRES(1);
 		return 0;
Index: trunk/src_plugins/shape/shape_dialog.c
===================================================================
--- trunk/src_plugins/shape/shape_dialog.c	(revision 36979)
+++ trunk/src_plugins/shape/shape_dialog.c	(revision 36980)
@@ -108,7 +108,7 @@
 	ctx_t *shp = caller_data;
 	rnd_coord_t dia = shp->dlg[shp->dia].val.crd;
 
-	if ((dia < 1) || (dia > (PCB->hidlib.size_x + PCB->hidlib.size_y)/4)) {
+	if ((dia < 1) || (dia > (rnd_dwg_get_size_x(&PCB->hidlib) + rnd_dwg_get_size_y(&PCB->hidlib))/4)) {
 		rnd_message(RND_MSG_ERROR, "Invalid diameter.\n");
 		return;
 	}
Index: trunk/src_plugins/sketch_route/sketch_route.c
===================================================================
--- trunk/src_plugins/sketch_route/sketch_route.c	(revision 36979)
+++ trunk/src_plugins/sketch_route/sketch_route.c	(revision 36980)
@@ -695,7 +695,7 @@
 	char name[256];
 
 	sk->cdt = malloc(sizeof(cdt_t));
-	cdt_init(sk->cdt, 0, 0, PCB->hidlib.size_x, -PCB->hidlib.size_y);
+	cdt_init(sk->cdt, 0, 0, PCB->hidlib.dwg.X2, -PCB->hidlib.dwg.Y2);
 	htpp_init(&sk->terminals, ptrhash, ptrkeyeq);
 	sk->wires.elem_constructor = vtwire_constructor;
 	sk->wires.elem_destructor = vtwire_destructor;
@@ -708,7 +708,7 @@
 
 	sk->spoke_tree = rnd_r_create_tree();
 
-	bbox.X1 = 0; bbox.Y1 = 0; bbox.X2 = PCB->hidlib.size_x; bbox.Y2 = PCB->hidlib.size_y;
+	bbox.X1 = PCB->hidlib.dwg.X1; bbox.Y1 = PCB->hidlib.dwg.Y1; bbox.X2 = PCB->hidlib.dwg.X2; bbox.Y2 = PCB->hidlib.dwg.Y2;
 	info.layer = layer;
 	info.sk = sk;
 	rnd_r_search(PCB->Data->padstack_tree, &bbox, NULL, r_search_cb, &info, NULL);
Index: trunk/src_plugins/smartdisperse/smartdisperse.c
===================================================================
--- trunk/src_plugins/smartdisperse/smartdisperse.c	(revision 36979)
+++ trunk/src_plugins/smartdisperse/smartdisperse.c	(revision 36980)
@@ -65,7 +65,7 @@
 	dx += PCB->hidlib.grid;
 
 	/* Figure out if this row has room.  If not, start a new row */
-	if (minx != GAP && GAP + sc->BoundingBox.X2 + dx > PCB->hidlib.size_x) {
+	if (minx != GAP && GAP + sc->BoundingBox.X2 + dx > PCB->hidlib.dwg.X2) {
 		miny = maxy + GAP;
 		minx = GAP;
 		place_subc(sc); /* recurse can't loop, now minx==GAP */
Index: trunk/tests/RTT/ref/arc_angles.ps.gz
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Index: trunk/tests/RTT/ref/arc_normal.ps.gz
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Index: trunk/tests/RTT/ref/arc_offpage.ps.gz
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Index: trunk/tests/RTT/ref/arc_sizes.ps.gz
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Index: trunk/tests/RTT/ref/comp1.ps.gz
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Index: trunk/tests/RTT/ref/comp1.svg
===================================================================
--- trunk/tests/RTT/ref/comp1.svg	(revision 36979)
+++ trunk/tests/RTT/ref/comp1.svg	(revision 36980)
@@ -34,7 +34,7 @@
  <path d="M 1.90500000 0.00000000 A 1.9050 1.9050 0 0 1 0.0000 1.9050" stroke-width="0.5080" stroke="#000000" stroke-linecap="round" fill="none"/>
  <line x1="2.5400" y1="5.7150" x2="2.5400" y2="3.1750" stroke-width="0.5080" stroke="#000000" stroke-linecap="round"/>
 </g>
-<mask id="comp_clip_1" maskUnits="userSpaceOnUse" x="0" y="0" width="12.7000" height="12.7000">
+<mask id="comp_clip_1" maskUnits="userSpaceOnUse" x="0.0000" y="0.0000" width="12.7000" height="12.7000">
  <polygon points="4.4450,0.6350 4.4450,4.4450 0.6350,4.4450 0.6350,0.6350 " stroke-width="0.010" stroke="#FFFFFF" fill="#FFFFFF"/>
  <polygon points="12.0650,0.6350 12.0650,12.0650 5.0800,12.0650 5.0800,0.6350 " stroke-width="0.010" stroke="#FFFFFF" fill="#FFFFFF"/>
  <polygon points="11.4300,1.2700 11.4300,11.4300 5.7150,11.4300 5.7150,1.2700 " stroke-width="0.010" stroke="#000000" fill="#000000"/>
@@ -53,7 +53,7 @@
 <!--normal-->
  <circle cx="6.3500" cy="1.9050" r="0.5000" stroke-width="0.0000" fill="#ffffff" stroke="none"/>
 </g>
-<mask id="comp_clip_2" maskUnits="userSpaceOnUse" x="0" y="0" width="12.7000" height="12.7000">
+<mask id="comp_clip_2" maskUnits="userSpaceOnUse" x="0.0000" y="0.0000" width="12.7000" height="12.7000">
 <circle cx="6.3500" cy="1.9050" r="0.5000" stroke-width="0.0000" fill="#FFFFFF" stroke="none"/>
 </mask>
 </defs>
@@ -67,7 +67,7 @@
 <g id="comp_pixel_3">
  <rect x="0.0000" y="0.0000" width="12.7000" height="12.7000" stroke-width="0.2540" stroke="#00868b" stroke-linecap="round" fill="none"/>
 </g>
-<mask id="comp_clip_3" maskUnits="userSpaceOnUse" x="0" y="0" width="12.7000" height="12.7000">
+<mask id="comp_clip_3" maskUnits="userSpaceOnUse" x="0.0000" y="0.0000" width="12.7000" height="12.7000">
  <rect x="0.0000" y="0.0000" width="12.7000" height="12.7000" stroke-width="0.2540" stroke="#FFFFFF" stroke-linecap="round" fill="none"/>
 </mask>
 </defs>
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