Index: parser.c
===================================================================
--- parser.c	(revision 36979)
+++ parser.c	(revision 36980)
@@ -650,12 +650,12 @@
 		}
 	}
 
-	width = max(PCB->hidlib.size_x, x_max - x_min + slack);
-	height = max(PCB->hidlib.size_y, y_max - y_min + slack);
+	width = max(rnd_dwg_get_size_x(&PCB->hidlib), x_max - x_min + slack);
+	height = max(rnd_dwg_get_size_y(&PCB->hidlib), y_max - y_min + slack);
 
 	/* resize if board too small */
-	if ((width > PCB->hidlib.size_x) || (height > PCB->hidlib.size_y))
-		pcb_board_resize(width, height, 0);
+	if ((width > PCB->hidlib.dwg.X2) || (height > PCB->hidlib.dwg.Y2))
+		pcb_board_resize(0, 0, width, height, 0);
 
 	return;
 
Index: write.c
===================================================================
--- write.c	(revision 36979)
+++ write.c	(revision 36980)
@@ -59,7 +59,7 @@
 /* pcb-rnd y-axis points down; hyperlynx y-axis points up */
 static rnd_coord_t flip(rnd_coord_t y)
 {
-	return (PCB->hidlib.size_y - y);
+	return (PCB->hidlib.dwg.Y2 - y);
 }
 
 static void hyp_grp_init(hyp_wr_t *wr)
@@ -371,10 +371,10 @@
 	if (!has_outline) {
 		/* implicit outline */
 		fprintf(wr->f, "* implicit outline derived from board width and height\n");
-		write_pr_line(wr, 0, 0, PCB->hidlib.size_x, 0);
-		write_pr_line(wr, 0, 0, 0, PCB->hidlib.size_y);
-		write_pr_line(wr, PCB->hidlib.size_x, 0, PCB->hidlib.size_x, PCB->hidlib.size_y);
-		write_pr_line(wr, 0, PCB->hidlib.size_y, PCB->hidlib.size_x, PCB->hidlib.size_y);
+		write_pr_line(wr, PCB->hidlib.dwg.X1, PCB->hidlib.dwg.Y1, PCB->hidlib.dwg.X2, PCB->hidlib.dwg.Y1);
+		write_pr_line(wr, PCB->hidlib.dwg.X1, PCB->hidlib.dwg.Y1, PCB->hidlib.dwg.X1, PCB->hidlib.dwg.Y2);
+		write_pr_line(wr, PCB->hidlib.dwg.X2, PCB->hidlib.dwg.Y1, PCB->hidlib.dwg.X2, PCB->hidlib.dwg.Y2);
+		write_pr_line(wr, PCB->hidlib.dwg.X1, PCB->hidlib.dwg.Y2, PCB->hidlib.dwg.X2, PCB->hidlib.dwg.Y2);
 	}
 	else { /* explicit outline */
 		for(i = 0, g = PCB->LayerGroups.grp; i < PCB->LayerGroups.len; i++,g++) {