Index: pcblib/parametric/acy
===================================================================
--- pcblib/parametric/acy	(revision 372)
+++ pcblib/parametric/acy	(revision 373)
@@ -8,7 +8,7 @@
 #@@params spacing,type,pol,dia
 
 #@@param:spacing spacing between the two pins
-#@@param:type silk symbol type: block, coil, core, core2, zigzag, line (optinal; default: block)
+#@@param:type silk symbol type: block, endcap, coil, core, core2, zigzag, line (optinal; default: block)
 #@@param:pol how to mark polarity: none, sign, bar, dot (optional; default: do not mark polarity)
 #@@param:dia body diameter - affects the silk rectangle (optional; default: spacing/12)
 #@@param:wiper silk symbol wiper type: none, parrow, aarrow, looparrow, thermistor (optinal; default: none)
Index: pcblib/parametric/acy.awk
===================================================================
--- pcblib/parametric/acy.awk	(revision 372)
+++ pcblib/parametric/acy.awk	(revision 373)
@@ -48,6 +48,23 @@
 	else if (P["type"] == "coil") {
 		wave(1, 4)
 	}
+	else if (P["type"] == "endcap") {
+		cl1 = len/9
+		cl2 = len/8
+		y1 = dia*1.2
+		y2 = dia
+		rarc = dia/5
+		element_line(sx1+cl2, y2, sx2-cl2, y2)
+		element_line(sx1+cl2, y2, sx1+cl1, y1)
+		element_line(sx2-cl2, y2, sx2-cl1, y1)
+		
+		element_line(sx1+cl2, -y2, sx2-cl2, -y2)
+		element_line(sx1+cl2, -y2, sx1+cl1, -y1)
+		element_line(sx2-cl2, -y2, sx2-cl1, -y1)
+
+		element_rectangle(sx1, y1, sx1+cl1, -y1, "right,NE,SE", rarc)
+		element_rectangle(sx2-cl1, y1, sx2, -y1, "left,NW,SW", rarc)
+	}
 	else if (P["type"] ~ "^core") {
 		wave(1, 4)
 		nlines = P["type"]