Index: work/bug_files/TODO/drc_clr.pcb
===================================================================
--- work/bug_files/TODO/drc_clr.pcb	(revision 37299)
+++ work/bug_files/TODO/drc_clr.pcb	(nonexistent)
@@ -1,74 +0,0 @@
-# release: pcb-rnd 3.1.1-dev
-
-# To read pcb files, the pcb version (or the git source date) must be >= the file version
-FileVersion[20070407]
-
-PCB["RVB-01v2" 160000 200000]
-
-Grid[500 0 0 1]
-Cursor[111000 192000 1000]
-PolyArea[3100.006203]
-Thermal[0.500000]
-DRC[1200 900 1000 700 1500 1000]
-Flags("nameonpcb,clearnew")
-Groups("4:6:1,c:3:2,s:7:5")
-Styles["Signal,1500,4000,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,1000,4000,2000,1000"]
-
-
-Attribute("PCB::grid::unit" "mm")
-Attribute("PCB::grid::size" "5.00mil")
-Attribute("PCB::loader" "geda/pcb - mainline (centimils)")
-
-Element["hidename" "MICS8" "CN2" "MICS8" 27500 124000 0 0 0 100 ""]
-(
-	Attribute("io_pcb::hidename_x" "6.9850 mm")
-	Attribute("io_pcb::hidename_y" "31.4960 mm")
-	Attribute("io_pcb::hidename_direction" "0")
-	Attribute("io_pcb::hidename_scale" "100")
-	Pin[5000 -10000 6000 2400 6000 3500 "2" "2" "clearline"]
-	Pin[15000 -10000 6000 2400 6000 3500 "4" "4" "clearline,thermal(1X)"]
-
-)
-Layer(1 "component")
-(
-)
-Layer(2 "solder")
-(
-	Polygon("clearpoly,lock")
-	(
-		[12000 169000] [146000 169000] [146000 12000] [12000 12000] 
-	)
-)
-Layer(3 "outline")
-(
-)
-Layer(4 "top-paste")
-(
-)
-Layer(5 "bottom-paste")
-(
-)
-Layer(6 "top-mask")
-(
-)
-Layer(7 "bottom-mask")
-(
-)
-Layer(8 "silk")
-(
-)
-Layer(9 "silk")
-(
-)
-
-NetList()
-(
-	Net("foo" "(unknown)")
-	(
-		Connect("CN2-2")
-	)
-	Net("bar" "(unknown)")
-	(
-		Connect("CN2-4")
-	)
-)