Index: 01_dc.cir.ref
===================================================================
--- 01_dc.cir.ref	(nonexistent)
+++ 01_dc.cir.ref	(revision 7893)
@@ -0,0 +1,17 @@
+.title sch-rnd export using export_spice
+
+*** circuit ***
+V1 in 0 DC 5V
+R1 in out1 2.2k
+R2 out1 out2 1k
+R3 out2 0 1k
+
+*** sch-rnd/export_spice: commands ***
+.control
+
+op
+print v(out1) v(out2)
+
+
+.endc
+.end
Index: 04_passive_tr.cir.ref
===================================================================
--- 04_passive_tr.cir.ref	(nonexistent)
+++ 04_passive_tr.cir.ref	(revision 7893)
@@ -0,0 +1,17 @@
+.title sch-rnd export using export_spice
+
+*** circuit ***
+V1 in 0 PULSE (0 5 1u 1u 1u 1 1)
+C1 mid 0 1u
+C2 out 0 1.2u
+R1 in mid 10k
+R2 mid out 15k
+
+*** sch-rnd/export_spice: commands ***
+.control
+
+tran 0.1ms 200ms
+plot v(in) v(mid) v(out) xlimit 0 200ms
+
+.endc
+.end
Index: 06_passive_ac.cir.ref
===================================================================
--- 06_passive_ac.cir.ref	(nonexistent)
+++ 06_passive_ac.cir.ref	(revision 7893)
@@ -0,0 +1,27 @@
+.title sch-rnd export using export_spice
+
+*** circuit ***
+V1 in 0 dc 0 ac 1
+C1 anon_net_3 0 1u
+C2 out 0 100n
+R1 in anon_net_3 10k
+R2 anon_net_3 out 1k
+
+*** sch-rnd/export_spice: commands ***
+.control
+
+ac dec 10 1 100k
+
+settype decibel out
+plot vdb(out) xlimit 1 100k ylabel 'small signal gain'
+
+settype phase out
+plot cph(out) xlimit 1 100k ylabel 'phase (in rad)'
+
+let outd = 180/PI*cph(out)
+settype phase outd
+plot outd xlimit 1 100k ylabel 'phase (in deg)'
+
+
+.endc
+.end
Index: 10_bjt_amp_tr.cir.ref
===================================================================
--- 10_bjt_amp_tr.cir.ref	(nonexistent)
+++ 10_bjt_amp_tr.cir.ref	(revision 7893)
@@ -0,0 +1,36 @@
+.title sch-rnd export using export_spice
+
+*** sch-rnd/export_spice: model card: _spice_model_card_bc817 ***
+* (C) 2023 Tibor 'Igor2' Palinkas
+* License: CC0 (no rights reserved): https://creativecommons.org/publicdomain/zero/1.0/
+* Source: based on Vishay's datasheet: https://archive.org/details/bc817_spice_vishay
+*
+.MODEL schrnd__spice_model_card_bc817 npn (
++ IS=2.43485e-13 VAF=10 BF=270 IKF=1.12487 NE=1.84302 ISE=7.17747e-12
++ IKR=0.149889 ISC=2.42047e-12 NC=3.94859 NR=1.04566 BR=2.51332 RC=0.407107
++ CJC=5.516e-11 FC=0.8 MJC=0.529364 VJC=0.4 CJE=5.10473e-11 MJE=0.412728
++ VJE=0.561234 TF=7.1424e-10 ITF=0.175457 VTF=1.86025 XTF=1.09929 RB=6.50128
++ IRB=0.1 RBM=0.1 RE=0.0814215 TR=1e-07
++ )
+
+
+
+*** circuit ***
+V1 in 0 SINE(0 0.01 1k)
+C1 in int_b 10u
+C2 int_c out 10u
+V2 Vcc 0 dc 5
+Q1 int_c int_b 0 schrnd__spice_model_card_bc817
+R1 Vcc int_b 87k
+R2 int_b 0 10k
+R3 Vcc int_c 33k
+R4 out 0 100k
+
+*** sch-rnd/export_spice: commands ***
+.control
+
+tran 1u 10m
+plot v(out) v(in)
+
+.endc
+.end
Index: 12_bjt_amp_ac.cir.ref
===================================================================
--- 12_bjt_amp_ac.cir.ref	(nonexistent)
+++ 12_bjt_amp_ac.cir.ref	(revision 7893)
@@ -0,0 +1,40 @@
+.title sch-rnd export using export_spice
+
+*** sch-rnd/export_spice: model card: _spice_model_card_bc817 ***
+* (C) 2023 Tibor 'Igor2' Palinkas
+* License: CC0 (no rights reserved): https://creativecommons.org/publicdomain/zero/1.0/
+* Source: based on Vishay's datasheet: https://archive.org/details/bc817_spice_vishay
+*
+.MODEL schrnd__spice_model_card_bc817 npn (
++ IS=2.43485e-13 VAF=10 BF=270 IKF=1.12487 NE=1.84302 ISE=7.17747e-12
++ IKR=0.149889 ISC=2.42047e-12 NC=3.94859 NR=1.04566 BR=2.51332 RC=0.407107
++ CJC=5.516e-11 FC=0.8 MJC=0.529364 VJC=0.4 CJE=5.10473e-11 MJE=0.412728
++ VJE=0.561234 TF=7.1424e-10 ITF=0.175457 VTF=1.86025 XTF=1.09929 RB=6.50128
++ IRB=0.1 RBM=0.1 RE=0.0814215 TR=1e-07
++ )
+
+
+
+*** circuit ***
+V1 in 0 dc 0 ac 0.1
+C1 in int_b 10u
+C2 int_c out 10u
+V2 Vcc 0 dc 5
+Q1 int_c int_b 0 schrnd__spice_model_card_bc817
+R1 Vcc int_b 87k
+R2 int_b 0 10k
+R3 Vcc int_c 33k
+R4 out 0 100k
+
+*** sch-rnd/export_spice: commands ***
+.control
+
+ac dec 10 1 1000k
+settype decibel out
+plot vdb(out) xlimit 1 1000k ylabel 'small signal gain'
+settype phase out
+plot cph(out) xlimit 1 1000k ylabel 'phase (in rad)'
+
+
+.endc
+.end
Index: 16_opamp_dc.cir.ref
===================================================================
--- 16_opamp_dc.cir.ref	(nonexistent)
+++ 16_opamp_dc.cir.ref	(revision 7893)
@@ -0,0 +1,84 @@
+.title sch-rnd export using export_spice
+
+*** sch-rnd/export_spice: model card: _spice_model_card_lm358 ***
+* lm358 - low power opamp model (single slot)
+*
+* (C) 2023 Tibor 'Igor2' Palinkas
+* License: CC0 (no rights reserved): https://creativecommons.org/publicdomain/zero/1.0/
+* Source: from ST's datasheet: https://archive.org/details/st-ts321
+* (st321 is reasonably close to lm358 for simple simulation cases; see
+* warnings on page 7)
+*
+*
+** CONNECTIONS:
+* 1 inverting input
+* 2 non-inverting INPUT
+* 3 output
+* 4 positive power supply
+* 5 negative power supply
+.SUBCKT schrnd__spice_model_card_lm358 1 2 3 4 5
+
+.MODEL MDTH D IS=1E-8 KF=3.104131E-15 CJO=10F
+
+* INPUT STAGE
+CIP 2 5 1.000000E-12
+CIN 1 5 1.000000E-12
+EIP 10 5 2 5 1
+EIN 16 5 1 5 1
+RIP 10 11 2.600000E+01
+RIN 15 16 2.600000E+01
+RIS 11 15 2.003862E+02
+DIP 11 12 MDTH 400E-12
+DIN 15 14 MDTH 400E-12
+VOFP 12 13 DC 0
+VOFN 13 14 DC 0
+IPOL 13 5 1.000000E-05
+CPS 11 15 3.783376E-09
+DINN 17 13 MDTH 400E-12
+VIN 17 5 0.000000e+00
+DINR 15 18 MDTH 400E-12
+VIP 4 18 2.000000E+00
+FCP 4 5 VOFP 3.400000E+01
+FCN 5 4 VOFN 3.400000E+01
+FIBP 2 5 VOFN 2.000000E-03
+FIBN 5 1 VOFP 2.000000E-03
+
+* AMPLIFYING STAGE
+FIP 5 19 VOFP 3.600000E+02
+FIN 5 19 VOFN 3.600000E+02
+RG1 19 5 3.652997E+06
+RG2 19 4 3.652997E+06
+CC 19 5 6.000000E-09
+DOPM 19 22 MDTH 400E-12
+DONM 21 19 MDTH 400E-12
+HOPM 22 28 VOUT 7.500000E+03
+VIPM 28 4 1.500000E+02
+HONM 21 27 VOUT 7.500000E+03
+VINM 5 27 1.500000E+02
+EOUT 26 23 19 5 1
+VOUT 23 5 0
+ROUT 26 3 20
+COUT 3 5 1.000000E-12
+DOP 19 25 MDTH 400E-12
+VOP 4 25 2.242230E+00
+DON 24 19 MDTH 400E-12
+VON 24 5 7.922301E-01
+.ENDS
+
+
+*** circuit ***
+V1 in 0 dc 0
+V2 Vcc 0 dc 5
+X_U1__1 anon_net_1 0 out Vcc Vneg schrnd__spice_model_card_lm358
+V3 0 Vneg dc 5
+R1 in anon_net_1 1k
+R2 anon_net_1 out 100k
+
+*** sch-rnd/export_spice: commands ***
+.control
+
+ dc V1 -50m 60m 2m
+plot v(in) v(out)
+
+.endc
+.end
Index: 18_opamp_ac.cir.ref
===================================================================
--- 18_opamp_ac.cir.ref	(nonexistent)
+++ 18_opamp_ac.cir.ref	(revision 7893)
@@ -0,0 +1,94 @@
+.title sch-rnd export using export_spice
+
+*** sch-rnd/export_spice: model card: _spice_model_card_lm358 ***
+* lm358 - low power opamp model (single slot)
+*
+* (C) 2023 Tibor 'Igor2' Palinkas
+* License: CC0 (no rights reserved): https://creativecommons.org/publicdomain/zero/1.0/
+* Source: from ST's datasheet: https://archive.org/details/st-ts321
+* (st321 is reasonably close to lm358 for simple simulation cases; see
+* warnings on page 7)
+*
+*
+** CONNECTIONS:
+* 1 inverting input
+* 2 non-inverting INPUT
+* 3 output
+* 4 positive power supply
+* 5 negative power supply
+.SUBCKT schrnd__spice_model_card_lm358 1 2 3 4 5
+
+.MODEL MDTH D IS=1E-8 KF=3.104131E-15 CJO=10F
+
+* INPUT STAGE
+CIP 2 5 1.000000E-12
+CIN 1 5 1.000000E-12
+EIP 10 5 2 5 1
+EIN 16 5 1 5 1
+RIP 10 11 2.600000E+01
+RIN 15 16 2.600000E+01
+RIS 11 15 2.003862E+02
+DIP 11 12 MDTH 400E-12
+DIN 15 14 MDTH 400E-12
+VOFP 12 13 DC 0
+VOFN 13 14 DC 0
+IPOL 13 5 1.000000E-05
+CPS 11 15 3.783376E-09
+DINN 17 13 MDTH 400E-12
+VIN 17 5 0.000000e+00
+DINR 15 18 MDTH 400E-12
+VIP 4 18 2.000000E+00
+FCP 4 5 VOFP 3.400000E+01
+FCN 5 4 VOFN 3.400000E+01
+FIBP 2 5 VOFN 2.000000E-03
+FIBN 5 1 VOFP 2.000000E-03
+
+* AMPLIFYING STAGE
+FIP 5 19 VOFP 3.600000E+02
+FIN 5 19 VOFN 3.600000E+02
+RG1 19 5 3.652997E+06
+RG2 19 4 3.652997E+06
+CC 19 5 6.000000E-09
+DOPM 19 22 MDTH 400E-12
+DONM 21 19 MDTH 400E-12
+HOPM 22 28 VOUT 7.500000E+03
+VIPM 28 4 1.500000E+02
+HONM 21 27 VOUT 7.500000E+03
+VINM 5 27 1.500000E+02
+EOUT 26 23 19 5 1
+VOUT 23 5 0
+ROUT 26 3 20
+COUT 3 5 1.000000E-12
+DOP 19 25 MDTH 400E-12
+VOP 4 25 2.242230E+00
+DON 24 19 MDTH 400E-12
+VON 24 5 7.922301E-01
+.ENDS
+
+
+*** circuit ***
+R5 anon_net_9 0 10k
+R4 out anon_net_9 250
+V1 in 0 dc 0 ac 0.1
+V2 Vcc 0 dc 5
+X_U1__1 out anon_net_13 out Vcc Vneg schrnd__spice_model_card_lm358
+V3 0 Vneg dc 5
+X_U1__2 anon_net_12 anon_net_9 anon_net_12 Vcc Vneg schrnd__spice_model_card_lm358
+C2 anon_net_10 anon_net_13 100n
+C3 anon_net_11 anon_net_12 200n
+C1 in anon_net_10 100n
+R1 in anon_net_11 1600
+R2 anon_net_11 anon_net_13 1600
+R3 anon_net_10 anon_net_12 800
+
+*** sch-rnd/export_spice: commands ***
+.control
+
+ac dec 10 1 1000k
+settype decibel out
+plot vdb(out) xlimit 1 1000k ylabel 'small signal gain'
+settype phase out
+plot cph(out) xlimit 1 1000k ylabel 'phase (in rad)'
+
+.endc
+.end
Index: 22_custom_sym.cir.ref
===================================================================
--- 22_custom_sym.cir.ref	(nonexistent)
+++ 22_custom_sym.cir.ref	(revision 7893)
@@ -0,0 +1,18 @@
+.title sch-rnd export using export_spice
+
+*** sch-rnd/export_spice: model card: U1 ***
+.MODEL schrnd_U1 D (IS=2f RS=3.4 N=2.2)
+
+*** circuit ***
+V1 in 0 SINE(0 20 1k)
+D_U1 0 out schrnd_U1
+R1 in out 100
+
+*** sch-rnd/export_spice: commands ***
+.control
+
+tran 1u 4m
+plot v(out) v(in)
+
+.endc
+.end
Index: 30_mixed.cir.ref
===================================================================
--- 30_mixed.cir.ref	(nonexistent)
+++ 30_mixed.cir.ref	(revision 7893)
@@ -0,0 +1,43 @@
+.title sch-rnd export using export_spice
+
+*** sch-rnd/export_spice: model card: U1 ***
+.MODEL schrnd_U1 d_xor (rise_delay=1.0e-6 fall_delay=2.0e-6
++ input_load=1.0e-12) 
+
+*** sch-rnd/export_spice: model card: bridge_dac_ttl ***
+* (C) 2023 Tibor 'Igor2' Palinkas
+* License: CC0 (no rights reserved): https://creativecommons.org/publicdomain/zero/1.0/
+*
+* source: https://www.allaboutcircuits.com/textbook/digital/chpt-3/logic-signal-voltage-levels/
+
+.MODEL bridge_dac_ttl dac_bridge(
++ out_low = 0 out_high = 5 out_undef = 1.4
++ input_load = 5.0e-12 t_rise = 50e-9 t_fall = 20e-9)
+
+
+*** sch-rnd/export_spice: model card: bridge_adc_ttl ***
+* (C) 2023 Tibor 'Igor2' Palinkas
+* License: CC0 (no rights reserved): https://creativecommons.org/publicdomain/zero/1.0/
+*
+* source: https://www.allaboutcircuits.com/textbook/digital/chpt-3/logic-signal-voltage-levels/
+
+.MODEL bridge_adc_ttl adc_bridge
++      (in_low=0.8 in_high=2.0 rise_delay=1.0e-12 fall_delay=1.0e-12)
+
+
+*** circuit ***
+A_U1 [br_bridge_adc_ttl_0 br_bridge_adc_ttl_1] br_bridge_dac_ttl_0 schrnd_U1
+V1 input1 0 PULSE (0 5 1 0.3 0.3 2 10)
+V2 input2 0 PULSE (0 5 2 0.3 0.3 2 4)
+A_sch_rnd_br_bridge_dac_ttl [br_bridge_dac_ttl_0] [output] bridge_dac_ttl
+A_sch_rnd_br_bridge_adc_ttl [input1 input2] [br_bridge_adc_ttl_0 br_bridge_adc_ttl_1] bridge_adc_ttl
+R1 output 0 100k
+
+*** sch-rnd/export_spice: commands ***
+.control
+
+tran 10ms 6s
+plot v(input1)+0.04 v(input2)+0.08 v(output) xlimit 0 6s
+
+.endc
+.end
Index: Makefile
===================================================================
--- Makefile	(nonexistent)
+++ Makefile	(revision 7893)
@@ -0,0 +1,11 @@
+all:
+
+test:
+	./test.sh
+
+clean:
+	touch dummy.cir.out
+	rm *.cir.out
+
+distclean: clean
+
Index: test.sh
===================================================================
--- test.sh	(nonexistent)
+++ test.sh	(revision 7893)
@@ -0,0 +1,31 @@
+#!/bin/sh
+root=../..
+tut=$root/doc/tutorial/simulation/raw
+src=$root/src/sch-rnd
+here=`pwd`
+refs=`ls *.cir.ref`
+
+bad=0
+all=0
+cd $src
+for n in $refs
+do
+	bn=${n%%.cir.ref}
+	./sch-rnd -x spice --view spice_raw --outfile $here/$bn.cir.out $tut/$bn.rs
+	diff $here/$bn.cir.ref $here/$bn.cir.out
+	if test $? = 0
+	then
+		rm $here/$bn.cir.out
+	else
+		echo "BROKEN spice: $n"
+		bad=$(($bad+1))
+	fi
+	all=$(($all+1))
+done
+
+if test $bad = 0
+then
+	echo "*** QC PASS ***"
+else
+	echo "Failed raw spice tests: $bad of $all"
+fi

Property changes on: test.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property