Index: simulation/raw/30_mixed.html
===================================================================
--- simulation/raw/30_mixed.html	(revision 7931)
+++ simulation/raw/30_mixed.html	(revision 7932)
@@ -4,17 +4,17 @@
 
 <h2> Scope </h2>
 <p>
-Mixed mode (analog + digital) simulation in time domain.
+Mixed mode (analog + digital) simulation in the time domain.
 
 <h2> The schematics </h2>
 <p>
 The input and the output of the circuit are analog, but there is a
-section of digital circuity in between (a xor gate). The simulator
+section of digital circuitry inbetween (a XOR gate). The simulator
 runs the analog sections in the normal fixed time stepping manner
 while the digital section is simulated based on events. This makes
 large digital circuits simulate much faster at the expense of tracking
-digital lines only using low/high/unknown states, not simulating
-transitions in details (rising/falling edges).
+digital lines only using low/high/unknown states, rather than simulating
+transitions in detail (rising/falling edges).
 <p>
 There are DAC and ADC converters inserted on the boundary of the
 analog and digital systems, using terminal attributes.
@@ -27,29 +27,29 @@
 
 <h2> Preparing for simulation </h2>
 <p>
-The xor gate is going to use ngspice's internal model called d_xor. The whole
+The XOR gate is going to use ngspice's internal model called d_xor. The whole
 model card is specified within the symbol, using the 
 <a href="../../../user/07_io/export_spice/model.html">spice/model_card</a>
 symbol attribute. The spice instance name must start with an 'A' for d_xor,
-while for other workflows the name U1 is more practical. This is fixed
-using the spice/prefix=A attribute.
+while for other workflows the name U1 is more practical. This is dealt with
+by using the spice/prefix=A attribute.
 <p>
-ADC converters are installed on the input terminals of the xor gate by
+ADC converters are installed on the input terminals of the XOR gate by
 setting the terminal attribute spice/bridge/model to bridge_adc_ttl, which
-is an sch-rnd stock spice model for TTL levels. Whenever spice/bridge/model
+is a sch-rnd stock spice model for TTL levels. Whenever spice/bridge/model
 is set on a terminal, target_spice will cut the original network connection
 of the terminal to insert a bridge component there. This component is
 not visible on the schematics, as it's specified in an attribute, but shows
 up in the abstract model for any view using target_spice.
 <p>
-In case of ngspice, only one bridge component is placed per model, because
-ngspice's bridge components can handle multiple inputs and outputs in an 1:1
+In the case of ngspice, only one bridge component is placed per model, because
+ngspice's bridge components can handle multiple inputs and outputs in a 1:1
 mapping.
 <p>
 (The sch-rnd user manual has more
 <a href="../../../user/07_io/export_spice/auto_bridge.html">details on bridging</a>)
 <p>
-The same bridging is done on the output terminal with model brirdge_dac_ttl.
+The same bridging is done on the output terminal with model bridge_dac_ttl.
 <p>
 On the input, two pulses V1 and V2 are installed to generate trapezoid
 signals with slow rising and falling edges. This is to demonstrate how ADC
@@ -61,8 +61,8 @@
 <p>
 This example executes a normal transient simulation. Since most signals
 are either low or high most of the time, they would overlap on the plot.
-To avoid confusion, slight y offsets are introduced using arithmetics,
-+0.0n.
+To avoid confusion, slight y offsets are introduced using an arithmetic
+expression, +0.0n.
 <pre>
 tran 10ms 6s
 plot v(input1)+0.04 v(input2)+0.08 v(output) xlimit 0 6s