Index: 06_features/simulation/index.html
===================================================================
--- 06_features/simulation/index.html (revision 8840)
+++ 06_features/simulation/index.html (revision 8841)
@@ -182,11 +182,43 @@
expect to work (std_cschem for things like the connect attribute, std_devmap
for the devmap and portmap mechanisms).
-
Low level simulation
+ Low level (raw) simulation
-TODO
+The low level, raw, simulation mechanism is used to enable an sch-rnd project
+to export to circuit simulation, e.g. spice. The high level simulation is
+built on top of the low level.
+
+The low level simulation consists of:
+
+ - a set of conventional attributes
+ and mechanisms built on top of them
+
- a set of the target_spice
+ plugin which tunes the compilation so that the abstract model is
+ usable for spice netlist export
+
- a view, normally called spice_raw, which uses target_spice as the target
+ engine
+
+
+The normal workflow is:
+
+ - set the view to spice_raw
+
- fill in all relevant attributes in symbols
+
- add extra symbols (e.g. voltage sources)
+
- compile and export using the spice export format
+
- maybe edit the exported file (e.g. gnucap requires that because of incompatibility)
+
- run a spice simulator on the exported file
+
+
+The extra symbols drawn for spice simulation may interfere with other workflows,
+e.g. if the same project is used as a soruce for a PCB workflow. There are
+multiple mechanisms to deal with this:
+
+ - the classic approach: draw spice-related extras on separate sheet and do not include that sheet in workflows different than spice
+
- use test benching or project stances in general to omit them
+
- the PCB workflow will automatically omit any component from the export that does not have a footprint attribute
+
- Test benching
+ Test benching
The test bench mechanism is responsible for selecting parts of the circuit
for simulation. Test benching operatos on project level. It is implemented