Index: work/alien_formats/eagle/eagle_bin/test_parser/eagle_bin.c =================================================================== --- work/alien_formats/eagle/eagle_bin/test_parser/eagle_bin.c (revision 9411) +++ work/alien_formats/eagle/eagle_bin/test_parser/eagle_bin.c (revision 9412) @@ -78,6 +78,29 @@ TERM }, }, + { PCB_EGKW_SECT_ALT_START, "alt_start", + { /* field match */ + TERM + }, + { /* subsection sizes */ +/* {2, 2, SS_DIRECT},*/ + {4, 4, SS_RECURSIVE_MINUS_1}, + TERM + }, + { /* attributes */ + {"subsecs", T_INT, 2, 2}, + {"numsecs", T_INT, 4, 4}, + {"subsecsMSB", T_INT, 3, 1}, + {"subsecsLSB", T_INT, 2, 1}, + {"numsecsMSB2", T_INT, 7, 1}, + {"numsecsMSB1", T_INT, 6, 1}, + {"numsecsMSB0", T_INT, 5, 1}, + {"numsecsLSB", T_INT, 4, 1}, + {"v1", T_INT, 8, 1}, + {"v2", T_INT, 9, 1}, + TERM + }, + }, { PCB_EGKW_SECT_UKNOWN11 }, { PCB_EGKW_SECT_GRID, "grid", { /* field match */ @@ -191,6 +214,22 @@ TERM }, }, + { PCB_EGKW_SECT_ALT_PACKAGES, "alt_packages", + { /* field match */ + TERM + }, + { /* subsection sizes */ + {4, 4, SS_RECURSIVE}, + TERM + }, + { /* attributes */ + {"subsects", T_INT, 4, 4}, + {"children", T_INT, 8, 2}, + {"desc", T_STR, 10, 6}, + {"libname", T_STR, 16, 8}, + TERM + }, + }, { PCB_EGKW_SECT_SCHEMASHEET, "schemasheet", { /* field match */ TERM @@ -232,6 +271,28 @@ TERM }, }, + { PCB_EGKW_SECT_ALT_BOARD, "alt_board", + { /* field match */ + TERM + }, + { /* subsection sizes */ + {12, 4, SS_RECURSIVE}, /* lib */ + {2, 2, SS_DIRECT}, /* globals */ + {16, 4, SS_RECURSIVE}, /* package refs */ + {20, 4, SS_RECURSIVE}, /* nets */ + TERM + }, + { /* attributes */ + {"minx", T_INT, 4, 2}, + {"miny", T_INT, 6, 2}, + {"maxx", T_INT, 8, 2}, + {"maxy", T_INT, 10, 2}, + {"defsubsecs", T_INT, 12, 4}, + {"pacsubsecs", T_INT, 16, 4}, + {"netsubsecs", T_INT, 20, 4}, + TERM + }, + }, { PCB_EGKW_SECT_BOARDNET, "boardnet", { /* field match */ TERM @@ -371,6 +432,60 @@ TERM }, }, + { PCB_EGKW_SECT_ALT_LINE, "alt_line", + { /* field match */ + TERM + }, + { /* subsection sizes */ + TERM + }, + { /* attributes */ + {"layer", T_INT, 3, 1}, + {"width_2", T_INT, 20, 2}, + {"stflags", T_BMB, 22, 0x20}, + {"linetype", T_INT, 23, 1}, + {"linetype_0_x1", T_INT, 4, 4}, + {"linetype_0_y1", T_INT, 8, 4}, + {"linetype_0_x2", T_INT, 12, 4}, + {"linetype_0_y2", T_INT, 16, 4}, + {"linetype_129_negflags", T_INT, 19, 1}, + {"linetype_129_c1", T_INT, 7, 1}, + {"linetype_129_c2", T_INT, 11, 1}, + {"linetype_129_c3", T_INT, 15, 1}, + {"linetype_129_x1", T_INT, 4, 3}, + {"linetype_129_y1", T_INT, 8, 3}, + {"linetype_129_x2", T_INT, 12, 3}, + {"linetype_129_y2", T_INT, 16, 3}, + TERM + }, + }, + { PCB_EGKW_SECT_ALT_ALT_LINE, "alt_alt_line", + { /* field match */ + TERM + }, + { /* subsection sizes */ + TERM + }, + { /* attributes */ + {"layer", T_INT, 3, 1}, + {"width_2", T_INT, 20, 2}, + {"stflags", T_BMB, 22, 0x20}, + {"linetype", T_INT, 23, 1}, + {"linetype_0_x1", T_INT, 4, 4}, + {"linetype_0_y1", T_INT, 8, 4}, + {"linetype_0_x2", T_INT, 12, 4}, + {"linetype_0_y2", T_INT, 16, 4}, + {"linetype_129_negflags", T_INT, 19, 1}, + {"linetype_129_c1", T_INT, 7, 1}, + {"linetype_129_c2", T_INT, 11, 1}, + {"linetype_129_c3", T_INT, 15, 1}, + {"linetype_129_x1", T_INT, 4, 3}, + {"linetype_129_y1", T_INT, 8, 3}, + {"linetype_129_x2", T_INT, 12, 3}, + {"linetype_129_y2", T_INT, 16, 3}, + TERM + }, + }, { PCB_EGKW_SECT_ARC, "arc", { /* field match */ TERM @@ -414,6 +529,22 @@ TERM }, }, + { PCB_EGKW_SECT_ALT_CIRCLE, "alt_circle", + { /* field match */ + TERM + }, + { /* subsection sizes */ + TERM + }, + { /* attributes */ + {"layer", T_INT, 3, 1}, + {"x1", T_INT, 4, 4}, + {"y1", T_INT, 8, 4}, + {"r", T_INT, 12, 4}, + {"width_2", T_INT, 20, 4}, + TERM + }, + }, { PCB_EGKW_SECT_RECTANGLE, "rectangle", { /* field match */ TERM @@ -431,6 +562,23 @@ TERM }, }, + { PCB_EGKW_SECT_ALT_RECTANGLE, "alt_rectangle", + { /* field match */ + TERM + }, + { /* subsection sizes */ + TERM + }, + { /* attributes */ + {"layer", T_INT, 3, 1}, + {"x1", T_INT, 4, 4}, + {"y1", T_INT, 8, 4}, + {"x2", T_INT, 12, 4}, + {"y3", T_INT, 16, 4}, + {"angle", T_INT, 20, 2}, + TERM + }, + }, { PCB_EGKW_SECT_JUNCTION, "junction", { /* field match */ TERM @@ -460,6 +608,20 @@ TERM }, }, + { PCB_EGKW_SECT_ALT_HOLE, "alt_hole", + { /* field match */ + TERM + }, + { /* subsection sizes */ + TERM + }, + { /* attributes */ + {"x", T_INT, 4, 4}, + {"y", T_INT, 8, 4}, + {"width_2", T_INT, 12, 4}, + TERM + }, + }, { PCB_EGKW_SECT_VIA, "via", { /* field match */ TERM @@ -478,6 +640,24 @@ TERM }, }, + { PCB_EGKW_SECT_ALT_VIA, "alt_via", + { /* field match */ + TERM + }, + { /* subsection sizes */ + TERM + }, + { /* attributes */ + {"shape", T_INT, 2, 1}, + {"x", T_INT, 4, 4}, + {"y", T_INT, 8, 4}, + {"drill_2", T_INT, 12, 2}, + {"diameter_2", T_INT, 14, 2}, + {"layers", T_INT, 16, 1}, /*not 1:1 mapping */ + {"stop", T_BMB, 17, 0x01}, + TERM + }, + }, { PCB_EGKW_SECT_PAD, "pad", { /* field match */ TERM @@ -499,6 +679,27 @@ TERM }, }, + { PCB_EGKW_SECT_ALT_PAD, "alt_pad", + { /* field match */ + TERM + }, + { /* subsection sizes */ + TERM + }, + { /* attributes */ + {"shape", T_INT, 2, 1}, + {"x", T_INT, 4, 4}, + {"y", T_INT, 8, 4}, + {"drill_2", T_INT, 12, 2}, + {"diameter_2", T_INT, 14, 2}, + {"angle", T_INT, 16, 2}, + {"stop", T_BMB, 18, 0x01}, + {"thermals", T_BMB, 18, 0x04}, + {"first", T_BMB, 18, 0x08}, + {"name", T_STR, 19, 5}, + TERM + }, + }, { PCB_EGKW_SECT_SMD, "smd", { /* field match */ TERM @@ -522,6 +723,29 @@ TERM }, }, + { PCB_EGKW_SECT_ALT_SMD, "alt_smd", + { /* field match */ + TERM + }, + { /* subsection sizes */ + TERM + }, + { /* attributes */ + {"roundness", T_INT, 2, 1}, + {"layer", T_INT, 3, 1}, + {"x", T_INT, 4, 4}, + {"y", T_INT, 8, 4}, + {"width_2", T_INT, 12, 2}, + {"height_2", T_INT, 14, 2}, + {"angle", T_UBF, 16, BITFIELD(2, 0, 11)}, + {"stop", T_BMB, 18, 0x01}, + {"cream", T_BMB, 18, 0x02}, + {"thermals", T_BMB, 18, 0x04}, + {"first", T_BMB, 18, 0x08}, + {"name", T_STR, 19, 5}, + TERM + }, + }, { PCB_EGKW_SECT_PIN, "pin", { /* field match */ TERM @@ -579,6 +803,25 @@ TERM }, }, + { PCB_EGKW_SECT_ALT_BOARDPACKAGE, "alt_boardpackage", + { /* field match */ + TERM + }, + { /* subsection sizes */ + {2, 2, SS_DIRECT}, + TERM + }, + { /* attributes */ + {"x", T_INT, 4, 4}, + {"y", T_INT, 8, 4}, + {"libno", T_INT, 12, 2}, + {"pacno", T_INT, 14, 2}, + {"angle", T_UBF, 16, BITFIELD(2, 0, 11)}, + {"mirrored", T_BMB, 17, 0x10}, + {"spin", T_BMB, 17, 0x40}, + TERM + }, + }, { PCB_EGKW_SECT_BOARDPACKAGE2, "boardpackage2", { /* field match */ TERM @@ -592,6 +835,19 @@ TERM }, }, + { PCB_EGKW_SECT_ALT_BOARDPACKAGE2, "alt_boardpackage2", + { /* field match */ + TERM + }, + { /* subsection sizes */ + TERM + }, + { /* attributes */ + {"name", T_STR, 2, 8}, + {"value", T_STR, 10, 14}, + TERM + }, + }, { PCB_EGKW_SECT_INSTANCE, "instance", { /* field match */ TERM @@ -637,6 +893,30 @@ TERM }, }, + { PCB_EGKW_SECT_ALT_TEXT, "alt_textbasesection", /* basic text block */ + { /* field match */ + TERM + }, + { /* subsection sizes */ + TERM + }, + { /* attributes */ + {"layer", T_INT, 3, 1}, + {"x", T_INT, 4, 4}, + {"y", T_INT, 8, 4}, + {"size", T_INT, 12, 2}, + {"ratio", T_UBF, 14, BITFIELD(2, 2, 6)}, + /*self._get_uint8_mask(14, 0x7c) >> 2 },*/ + {"angle" , T_UBF, 16, BITFIELD(2, 0, 11)}, + /*self._get_uint16_mask(16, 0x0fff)*/ + {"mirrored" , T_UBF, 16, BITFIELD(2, 12, 12)}, + /*bool(self._get_uint16_mask(16, 0x1000))*/ + {"spin" , T_UBF, 16, BITFIELD(2, 14, 14)}, + /*bool(self._get_uint16_mask(16, 0x4000))*/ + {"textfield", T_STR, 18, 5}, + TERM + }, + }, { PCB_EGKW_SECT_NETBUSLABEL, "netbuslabel", /* text base section equiv. */ { /* field match */ TERM @@ -685,6 +965,54 @@ TERM }, }, + { PCB_EGKW_SECT_ALT_SMASHEDNAME, "alt_smashedname", /* text base section equiv. */ + { /* field match */ + TERM + }, + { /* subsection sizes */ + TERM + }, + { /* attributes */ + {"layer", T_INT, 3, 1}, + {"x", T_INT, 4, 4}, + {"y", T_INT, 8, 4}, + {"size", T_INT, 12, 2}, + {"ratio", T_UBF, 14, BITFIELD(2, 2, 6)}, + /*self._get_uint8_mask(14, 0x7c) >> 2 },*/ + {"angle" , T_UBF, 16, BITFIELD(2, 0, 11)}, + /*self._get_uint16_mask(16, 0x0fff)*/ + {"mirrored" , T_UBF, 16, BITFIELD(2, 12, 12)}, + /*bool(self._get_uint16_mask(16, 0x1000))*/ + {"spin" , T_UBF, 16, BITFIELD(2, 14, 14)}, + /*bool(self._get_uint16_mask(16, 0x4000))*/ + {"textfield", T_STR, 18, 5}, + TERM + }, + }, + { PCB_EGKW_SECT_ALT_ALT_SMASHEDNAME, "alt_alt_smashedname", /* text base section equiv. */ + { /* field match */ + TERM + }, + { /* subsection sizes */ + TERM + }, + { /* attributes */ + {"layer", T_INT, 3, 1}, + {"x", T_INT, 4, 4}, + {"y", T_INT, 8, 4}, + {"size", T_INT, 12, 2}, + {"ratio", T_UBF, 14, BITFIELD(2, 2, 6)}, + /*self._get_uint8_mask(14, 0x7c) >> 2 },*/ + {"angle" , T_UBF, 16, BITFIELD(2, 0, 11)}, + /*self._get_uint16_mask(16, 0x0fff)*/ + {"mirrored" , T_UBF, 16, BITFIELD(2, 12, 12)}, + /*bool(self._get_uint16_mask(16, 0x1000))*/ + {"spin" , T_UBF, 16, BITFIELD(2, 14, 14)}, + /*bool(self._get_uint16_mask(16, 0x4000))*/ + {"textfield", T_STR, 18, 5}, + TERM + }, + }, { PCB_EGKW_SECT_SMASHEDVALUE, "smashedvalue", /* text base section equiv. */ { /* field match */ TERM @@ -709,6 +1037,30 @@ TERM }, }, + { PCB_EGKW_SECT_ALT_SMASHEDVALUE, "alt_smashedvalue", /* text base section equiv. */ + { /* field match */ + TERM + }, + { /* subsection sizes */ + TERM + }, + { /* attributes */ + {"layer", T_INT, 3, 1}, + {"x", T_INT, 4, 4}, + {"y", T_INT, 8, 4}, + {"size", T_INT, 12, 2}, + {"ratio", T_UBF, 14, BITFIELD(2, 2, 6)}, + /*self._get_uint8_mask(14, 0x7c) >> 2 },*/ + {"angle" , T_UBF, 16, BITFIELD(2, 0, 11)}, + /*self._get_uint16_mask(16, 0x0fff)*/ + {"mirrored" , T_UBF, 16, BITFIELD(2, 12, 12)}, + /*bool(self._get_uint16_mask(16, 0x1000))*/ + {"spin" , T_UBF, 16, BITFIELD(2, 14, 14)}, + /*bool(self._get_uint16_mask(16, 0x4000))*/ + {"textfield", T_STR, 18, 5}, + TERM + }, + }, { PCB_EGKW_SECT_PACKAGEVARIANT }, { PCB_EGKW_SECT_DEVICE }, { PCB_EGKW_SECT_PART }, @@ -728,6 +1080,19 @@ TERM }, }, + { PCB_EGKW_SECT_ALT_BOARDCONNECTION, "alt_boardconnection", + { /* field match */ + TERM + }, + { /* subsection sizes */ + TERM + }, + { /* attributes */ + {"partnumber", T_INT, 4, 2}, + {"pin", T_INT, 6, 2}, + TERM + }, + }, { PCB_EGKW_SECT_SMASHEDPART, "smashedpart", /* same as text basesection */ { /* field match */ TERM @@ -800,6 +1165,30 @@ TERM }, }, + { PCB_EGKW_SECT_ALT_ATTRIBUTE, "alt_attribute", /* same as text basesection */ + { /* field match */ + TERM + }, + { /* subsection sizes */ + TERM + }, + { /* attributes */ + {"layer", T_INT, 3, 1}, + {"x", T_INT, 4, 4}, + {"y", T_INT, 8, 4}, + {"size", T_INT, 12, 2}, + {"ratio", T_UBF, 14, BITFIELD(2, 2, 6)}, + /*self._get_uint8_mask(14, 0x7c) >> 2 },*/ + {"angle" , T_UBF, 16, BITFIELD(2, 0, 11)}, + /*self._get_uint16_mask(16, 0x0fff)*/ + {"mirrored" , T_UBF, 16, BITFIELD(2, 12, 12)}, + /*bool(self._get_uint16_mask(16, 0x1000))*/ + {"spin" , T_UBF, 16, BITFIELD(2, 14, 14)}, + /*bool(self._get_uint16_mask(16, 0x4000))*/ + {"textfield", T_STR, 18, 5}, + TERM + }, + }, { PCB_EGKW_SECT_ATTRIBUTEVALUE, "attribute-value", { /* field match */ TERM Index: work/alien_formats/eagle/eagle_bin/test_parser/eagle_bin.h =================================================================== --- work/alien_formats/eagle/eagle_bin/test_parser/eagle_bin.h (revision 9411) +++ work/alien_formats/eagle/eagle_bin/test_parser/eagle_bin.h (revision 9412) @@ -2,6 +2,7 @@ typedef enum pcb_eagle_binkw_s { PCB_EGKW_SECT_START = 0x1000, + PCB_EGKW_SECT_ALT_START = 0x1080, PCB_EGKW_SECT_UKNOWN11 = 0x1100, PCB_EGKW_SECT_GRID = 0x1200, PCB_EGKW_SECT_LAYER = 0x1300, @@ -10,8 +11,10 @@ PCB_EGKW_SECT_DEVICES = 0x1700, PCB_EGKW_SECT_SYMBOLS = 0x1800, PCB_EGKW_SECT_PACKAGES = 0x1900, + PCB_EGKW_SECT_ALT_PACKAGES = 0x1980, PCB_EGKW_SECT_SCHEMASHEET = 0x1a00, PCB_EGKW_SECT_BOARD = 0x1b00, + PCB_EGKW_SECT_ALT_BOARD = 0x1b80, PCB_EGKW_SECT_BOARDNET = 0x1c00, PCB_EGKW_SECT_SYMBOL = 0x1d00, PCB_EGKW_SECT_PACKAGE = 0x1e00, @@ -19,23 +22,37 @@ PCB_EGKW_SECT_PATH = 0x2000, PCB_EGKW_SECT_POLYGON = 0x2100, PCB_EGKW_SECT_LINE = 0x2200, + PCB_EGKW_SECT_ALT_LINE = 0x2280, + PCB_EGKW_SECT_ALT_ALT_LINE = 0x2290, PCB_EGKW_SECT_ARC = 0x2400, PCB_EGKW_SECT_CIRCLE = 0x2500, + PCB_EGKW_SECT_ALT_CIRCLE = 0x2580, PCB_EGKW_SECT_RECTANGLE = 0x2600, + PCB_EGKW_SECT_ALT_RECTANGLE = 0x2680, PCB_EGKW_SECT_JUNCTION = 0x2700, PCB_EGKW_SECT_HOLE = 0x2800, + PCB_EGKW_SECT_ALT_HOLE = 0x2880, PCB_EGKW_SECT_VIA = 0x2900, + PCB_EGKW_SECT_ALT_VIA = 0x2980, PCB_EGKW_SECT_PAD = 0x2a00, + PCB_EGKW_SECT_ALT_PAD = 0x2a80, PCB_EGKW_SECT_SMD = 0x2b00, + PCB_EGKW_SECT_ALT_SMD = 0x2b80, PCB_EGKW_SECT_PIN = 0x2c00, PCB_EGKW_SECT_GATE = 0x2d00, PCB_EGKW_SECT_BOARDPACKAGE = 0x2e00, + PCB_EGKW_SECT_ALT_BOARDPACKAGE = 0x2e80, PCB_EGKW_SECT_BOARDPACKAGE2 = 0x2f00, + PCB_EGKW_SECT_ALT_BOARDPACKAGE2 = 0x2f80, PCB_EGKW_SECT_INSTANCE = 0x3000, PCB_EGKW_SECT_TEXT = 0x3100, + PCB_EGKW_SECT_ALT_TEXT = 0x3180, PCB_EGKW_SECT_NETBUSLABEL = 0x3300, PCB_EGKW_SECT_SMASHEDNAME = 0x3400, + PCB_EGKW_SECT_ALT_SMASHEDNAME = 0x3480, + PCB_EGKW_SECT_ALT_ALT_SMASHEDNAME = 0x348c, PCB_EGKW_SECT_SMASHEDVALUE = 0x3500, + PCB_EGKW_SECT_ALT_SMASHEDVALUE = 0x3580, PCB_EGKW_SECT_PACKAGEVARIANT = 0x3600, PCB_EGKW_SECT_DEVICE = 0x3700, PCB_EGKW_SECT_PART = 0x3800, @@ -43,9 +60,11 @@ PCB_EGKW_SECT_VARIANTCONNECTIONS = 0x3c00, PCB_EGKW_SECT_SCHEMACONNECTION = 0x3d00, PCB_EGKW_SECT_BOARDCONNECTION = 0x3e00, + PCB_EGKW_SECT_ALT_BOARDCONNECTION = 0x3e80, PCB_EGKW_SECT_SMASHEDPART = 0x3f00, PCB_EGKW_SECT_SMASHEDGATE = 0x4000, PCB_EGKW_SECT_ATTRIBUTE = 0x4100, + PCB_EGKW_SECT_ALT_ATTRIBUTE = 0x4180, PCB_EGKW_SECT_ATTRIBUTEVALUE = 0x4200, PCB_EGKW_SECT_FRAME = 0x4300, PCB_EGKW_SECT_SMASHEDXREF = 0x4400,