Index: eagle_bin/test_parser/eagle_bin.c =================================================================== --- eagle_bin/test_parser/eagle_bin.c (revision 9422) +++ eagle_bin/test_parser/eagle_bin.c (revision 9423) @@ -139,6 +139,25 @@ TERM }, }, + { PCB_EGKW_SECT_ALT_LAYER, "alt_layer", + { /* field match */ + TERM + }, + { /* subsection sizes */ + TERM + }, + { /* attributes */ + {"side", T_BMB, 2, 0x10}, + {"visible", T_UBF, 2, BITFIELD(1, 2, 3)}, + {"available", T_BMB, 2, 0x02}, + {"layer",T_INT, 3, 1}, + {"other",T_INT, 4, 1}, + {"fill", T_UBF, 5, BITFIELD(1, 0, 3)}, + {"color",T_UBF, 6, BITFIELD(1, 0, 5)}, + {"name", T_STR, 15, 9}, + TERM + }, + }, { PCB_EGKW_SECT_SCHEMA, "schema", { /* field match */ TERM @@ -315,6 +334,28 @@ TERM }, }, + { PCB_EGKW_SECT_ALT_ALT_ALT_BOARD, "alt_alt_alt_board", + { /* field match */ + TERM + }, + { /* subsection sizes */ + {12, 4, SS_RECURSIVE}, /* lib */ + {2, 2, SS_DIRECT}, /* globals */ + {16, 4, SS_RECURSIVE}, /* package refs */ + {20, 4, SS_RECURSIVE}, /* nets */ + TERM + }, + { /* attributes */ + {"minx", T_INT, 4, 2}, + {"miny", T_INT, 6, 2}, + {"maxx", T_INT, 8, 2}, + {"maxy", T_INT, 10, 2}, + {"defsubsecs", T_INT, 12, 4}, + {"pacsubsecs", T_INT, 16, 4}, + {"netsubsecs", T_INT, 20, 4}, + TERM + }, + }, { PCB_EGKW_SECT_BOARDNET, "boardnet", { /* field match */ TERM @@ -353,6 +394,44 @@ TERM }, }, + { PCB_EGKW_SECT_ALT_ALT_BOARDNET, "alt_alt_boardnet", + { /* field match */ + TERM + }, + { /* subsection sizes */ + {2, 2, SS_DIRECT}, + TERM + }, + { /* attributes */ + {"minx", T_INT, 4, 2}, + {"miny", T_INT, 6, 2}, + {"maxx", T_INT, 8, 2}, + {"maxy", T_INT, 10, 2}, + {"airwires", T_BMB, 12, 0x02}, + {"netclass", T_UBF, 13, BITFIELD(1, 0, 3)}, + {"name", T_INT, 16, 8}, + TERM + }, + }, + { PCB_EGKW_SECT_ALT_ALT_ALT_BOARDNET, "alt_alt_alt_boardnet", + { /* field match */ + TERM + }, + { /* subsection sizes */ + {2, 2, SS_DIRECT}, + TERM + }, + { /* attributes */ + {"minx", T_INT, 4, 2}, + {"miny", T_INT, 6, 2}, + {"maxx", T_INT, 8, 2}, + {"maxy", T_INT, 10, 2}, + {"airwires", T_BMB, 12, 0x02}, + {"netclass", T_UBF, 13, BITFIELD(1, 0, 3)}, + {"name", T_INT, 16, 8}, + TERM + }, + }, { PCB_EGKW_SECT_SYMBOL, "symbol", { /* field match */ TERM @@ -554,6 +633,114 @@ TERM }, }, + { PCB_EGKW_SECT_ALT_ALT_ALT_ALT_LINE, "alt_alt_alt_alt_line", + { /* field match */ + TERM + }, + { /* subsection sizes */ + TERM + }, + { /* attributes */ + {"layer", T_INT, 3, 1}, + {"width_2", T_INT, 20, 2}, + {"stflags", T_BMB, 22, 0x20}, + {"linetype", T_INT, 23, 1}, + {"linetype_0_x1", T_INT, 4, 4}, + {"linetype_0_y1", T_INT, 8, 4}, + {"linetype_0_x2", T_INT, 12, 4}, + {"linetype_0_y2", T_INT, 16, 4}, + {"linetype_129_negflags", T_INT, 19, 1}, + {"linetype_129_c1", T_INT, 7, 1}, + {"linetype_129_c2", T_INT, 11, 1}, + {"linetype_129_c3", T_INT, 15, 1}, + {"linetype_129_x1", T_INT, 4, 3}, + {"linetype_129_y1", T_INT, 8, 3}, + {"linetype_129_x2", T_INT, 12, 3}, + {"linetype_129_y2", T_INT, 16, 3}, + TERM + }, + }, + { PCB_EGKW_SECT_ALT_ALT_ALT_ALT_ALT_LINE, "alt_alt_alt_alt_alt_line", + { /* field match */ + TERM + }, + { /* subsection sizes */ + TERM + }, + { /* attributes */ + {"layer", T_INT, 3, 1}, + {"width_2", T_INT, 20, 2}, + {"stflags", T_BMB, 22, 0x20}, + {"linetype", T_INT, 23, 1}, + {"linetype_0_x1", T_INT, 4, 4}, + {"linetype_0_y1", T_INT, 8, 4}, + {"linetype_0_x2", T_INT, 12, 4}, + {"linetype_0_y2", T_INT, 16, 4}, + {"linetype_129_negflags", T_INT, 19, 1}, + {"linetype_129_c1", T_INT, 7, 1}, + {"linetype_129_c2", T_INT, 11, 1}, + {"linetype_129_c3", T_INT, 15, 1}, + {"linetype_129_x1", T_INT, 4, 3}, + {"linetype_129_y1", T_INT, 8, 3}, + {"linetype_129_x2", T_INT, 12, 3}, + {"linetype_129_y2", T_INT, 16, 3}, + TERM + }, + }, + { PCB_EGKW_SECT_ALT_ALT_ALT_ALT_ALT_ALT_LINE, "alt_alt_alt_alt_alt_alt_line", + { /* field match */ + TERM + }, + { /* subsection sizes */ + TERM + }, + { /* attributes */ + {"layer", T_INT, 3, 1}, + {"width_2", T_INT, 20, 2}, + {"stflags", T_BMB, 22, 0x20}, + {"linetype", T_INT, 23, 1}, + {"linetype_0_x1", T_INT, 4, 4}, + {"linetype_0_y1", T_INT, 8, 4}, + {"linetype_0_x2", T_INT, 12, 4}, + {"linetype_0_y2", T_INT, 16, 4}, + {"linetype_129_negflags", T_INT, 19, 1}, + {"linetype_129_c1", T_INT, 7, 1}, + {"linetype_129_c2", T_INT, 11, 1}, + {"linetype_129_c3", T_INT, 15, 1}, + {"linetype_129_x1", T_INT, 4, 3}, + {"linetype_129_y1", T_INT, 8, 3}, + {"linetype_129_x2", T_INT, 12, 3}, + {"linetype_129_y2", T_INT, 16, 3}, + TERM + }, + }, + { PCB_EGKW_SECT_ALT_ALT_ALT_ALT_ALT_ALT_ALT_LINE, "alt_alt_alt_alt_alt_alt_alt_line", + { /* field match */ + TERM + }, + { /* subsection sizes */ + TERM + }, + { /* attributes */ + {"layer", T_INT, 3, 1}, + {"width_2", T_INT, 20, 2}, + {"stflags", T_BMB, 22, 0x20}, + {"linetype", T_INT, 23, 1}, + {"linetype_0_x1", T_INT, 4, 4}, + {"linetype_0_y1", T_INT, 8, 4}, + {"linetype_0_x2", T_INT, 12, 4}, + {"linetype_0_y2", T_INT, 16, 4}, + {"linetype_129_negflags", T_INT, 19, 1}, + {"linetype_129_c1", T_INT, 7, 1}, + {"linetype_129_c2", T_INT, 11, 1}, + {"linetype_129_c3", T_INT, 15, 1}, + {"linetype_129_x1", T_INT, 4, 3}, + {"linetype_129_y1", T_INT, 8, 3}, + {"linetype_129_x2", T_INT, 12, 3}, + {"linetype_129_y2", T_INT, 16, 3}, + TERM + }, + }, { PCB_EGKW_SECT_ARC, "arc", { /* field match */ TERM @@ -909,6 +1096,25 @@ TERM }, }, + { PCB_EGKW_SECT_ALT_ALT_ALT_BOARDPACKAGE, "alt_alt_alt_boardpackage", + { /* field match */ + TERM + }, + { /* subsection sizes */ + {2, 2, SS_DIRECT}, + TERM + }, + { /* attributes */ + {"x", T_INT, 4, 4}, + {"y", T_INT, 8, 4}, + {"libno", T_INT, 12, 2}, + {"pacno", T_INT, 14, 2}, + {"angle", T_UBF, 16, BITFIELD(2, 0, 11)}, + {"mirrored", T_BMB, 17, 0x10}, + {"spin", T_BMB, 17, 0x40}, + TERM + }, + }, { PCB_EGKW_SECT_BOARDPACKAGE2, "boardpackage2", { /* field match */ TERM Index: eagle_bin/test_parser/eagle_bin.h =================================================================== --- eagle_bin/test_parser/eagle_bin.h (revision 9422) +++ eagle_bin/test_parser/eagle_bin.h (revision 9423) @@ -6,6 +6,7 @@ PCB_EGKW_SECT_UKNOWN11 = 0x1100, PCB_EGKW_SECT_GRID = 0x1200, PCB_EGKW_SECT_LAYER = 0x1300, + PCB_EGKW_SECT_ALT_LAYER = 0x1380, PCB_EGKW_SECT_SCHEMA = 0x1400, PCB_EGKW_SECT_LIBRARY = 0x1500, PCB_EGKW_SECT_DEVICES = 0x1700, @@ -14,10 +15,13 @@ PCB_EGKW_SECT_ALT_PACKAGES = 0x1980, PCB_EGKW_SECT_SCHEMASHEET = 0x1a00, PCB_EGKW_SECT_BOARD = 0x1b00, - PCB_EGKW_SECT_ALT_BOARD = 0x1b80, - PCB_EGKW_SECT_ALT_ALT_BOARD = 0x1b08, + PCB_EGKW_SECT_ALT_BOARD = 0x1b40, + PCB_EGKW_SECT_ALT_ALT_BOARD = 0x1b80, + PCB_EGKW_SECT_ALT_ALT_ALT_BOARD = 0x1b08, PCB_EGKW_SECT_BOARDNET = 0x1c00, PCB_EGKW_SECT_ALT_BOARDNET = 0x1c04, + PCB_EGKW_SECT_ALT_ALT_BOARDNET = 0x1c40, + PCB_EGKW_SECT_ALT_ALT_ALT_BOARDNET = 0x1c48, PCB_EGKW_SECT_SYMBOL = 0x1d00, PCB_EGKW_SECT_PACKAGE = 0x1e00, PCB_EGKW_SECT_SCHEMANET = 0x1f00, @@ -27,6 +31,10 @@ PCB_EGKW_SECT_ALT_LINE = 0x2280, PCB_EGKW_SECT_ALT_ALT_LINE = 0x2290, PCB_EGKW_SECT_ALT_ALT_ALT_LINE = 0x229c, + PCB_EGKW_SECT_ALT_ALT_ALT_ALT_LINE = 0x22a0, + PCB_EGKW_SECT_ALT_ALT_ALT_ALT_ALT_LINE = 0x22a8, + PCB_EGKW_SECT_ALT_ALT_ALT_ALT_ALT_ALT_LINE = 0x228c, + PCB_EGKW_SECT_ALT_ALT_ALT_ALT_ALT_ALT_ALT_LINE = 0x2288, PCB_EGKW_SECT_ARC = 0x2400, PCB_EGKW_SECT_CIRCLE = 0x2500, PCB_EGKW_SECT_ALT_CIRCLE = 0x2580, @@ -44,8 +52,9 @@ PCB_EGKW_SECT_PIN = 0x2c00, PCB_EGKW_SECT_GATE = 0x2d00, PCB_EGKW_SECT_BOARDPACKAGE = 0x2e00, - PCB_EGKW_SECT_ALT_BOARDPACKAGE = 0x2e80, - PCB_EGKW_SECT_ALT_ALT_BOARDPACKAGE = 0x2e0c, + PCB_EGKW_SECT_ALT_BOARDPACKAGE = 0x2e20, + PCB_EGKW_SECT_ALT_ALT_BOARDPACKAGE = 0x2e80, + PCB_EGKW_SECT_ALT_ALT_ALT_BOARDPACKAGE = 0x2e0c, PCB_EGKW_SECT_BOARDPACKAGE2 = 0x2f00, PCB_EGKW_SECT_ALT_BOARDPACKAGE2 = 0x2f80, PCB_EGKW_SECT_INSTANCE = 0x3000,