Index: work/alien_formats/eagle/eagle_bin/test_parser/eagle_bin.c =================================================================== --- work/alien_formats/eagle/eagle_bin/test_parser/eagle_bin.c (revision 9544) +++ work/alien_formats/eagle/eagle_bin/test_parser/eagle_bin.c (revision 9545) @@ -46,7 +46,7 @@ } attrs_t; typedef struct { - unsigned int cmd;/* rule matches only if block[0] == cmd */ + unsigned int cmd, cmd_mask;/* rule matches only if block[0] == cmd */ char *name; fmatch_t fmatch[4]; /* rule matches only if all fmatch integer fields match their val */ subsect_t subs[8];/* how to extract number of subsections (direct children) */ @@ -56,7 +56,7 @@ #define TERM {0} static const pcb_eagle_script_t pcb_eagle_script[] = { - { PCB_EGKW_SECT_START, "start", + { PCB_EGKW_SECT_START, 0xFFFF, "start", { /* field match */ TERM }, @@ -79,7 +79,7 @@ TERM }, }, - { PCB_EGKW_SECT_ALT_START, "alt_start", + { PCB_EGKW_SECT_ALT_START, 0xFFFF, "alt_start", { /* field match */ TERM }, @@ -102,8 +102,8 @@ TERM }, }, - { PCB_EGKW_SECT_UKNOWN11 }, - { GRID, "grid", + { PCB_EGKW_SECT_UKNOWN11, 0xFFFF }, + { GRID, 0xFFFF, "grid", { /* field match */ TERM }, @@ -121,7 +121,7 @@ TERM }, }, - { LAYERS, "layers", + { LAYERS, 0xFFFF, "layers", { /* field match */ TERM }, @@ -140,7 +140,7 @@ TERM }, }, - { ALT_LAYERS, "alt_layers", + { ALT_LAYERS, 0xFFFF, "alt_layers", { /* field match */ TERM }, @@ -159,7 +159,7 @@ TERM }, }, - { PCB_EGKW_SECT_SCHEMA, "schema", + { PCB_EGKW_SECT_SCHEMA, 0xFFFF, "schema", { /* field match */ TERM }, @@ -174,7 +174,7 @@ TERM }, }, - { LIBRARY, "library", + { LIBRARY, 0xFFFF, "library", { /* field match */ TERM }, @@ -190,7 +190,7 @@ TERM }, }, - { PCB_EGKW_SECT_DEVICES, "devices", + { PCB_EGKW_SECT_DEVICES, 0xFFFF, "devices", { /* field match */ TERM }, @@ -204,7 +204,7 @@ TERM }, }, - { PCB_EGKW_SECT_SYMBOL, "symbols", + { PCB_EGKW_SECT_SYMBOL, 0xFFFF, "symbols", { /* field match */ TERM }, @@ -218,7 +218,7 @@ TERM }, }, - { PACKAGES, "packages", + { PACKAGES, 0xFFFF, "packages", { /* field match */ TERM }, @@ -234,7 +234,7 @@ TERM }, }, - { ALT_PACKAGES, "alt_packages", + { ALT_PACKAGES, 0xFFFF, "alt_packages", { /* field match */ TERM }, @@ -250,7 +250,7 @@ TERM }, }, - { ALT_ALT_PACKAGES, "alt_alt_packages", + { ALT_ALT_PACKAGES, 0xFFFF, "alt_alt_packages", { /* field match */ TERM }, @@ -266,7 +266,7 @@ TERM }, }, - { PCB_EGKW_SECT_SCHEMASHEET, "schemasheet", + { PCB_EGKW_SECT_SCHEMASHEET, 0xFFFF, "schemasheet", { /* field match */ TERM }, @@ -285,7 +285,7 @@ TERM }, }, - { BOARD, "board", + { BOARD, 0xFFFF, "board", { /* field match */ TERM }, @@ -307,7 +307,7 @@ TERM }, }, - { ALT_BOARD, "alt_board", + { ALT_BOARD, 0xFFFF, "alt_board", { /* field match */ TERM }, @@ -329,7 +329,7 @@ TERM }, }, - { ALT_ALT_BOARD, "alt_alt_board", + { ALT_ALT_BOARD, 0xFFFF, "alt_alt_board", { /* field match */ TERM }, @@ -351,7 +351,7 @@ TERM }, }, - { ALT_ALT_ALT_BOARD, "alt_alt_alt_board", + { ALT_ALT_ALT_BOARD, 0xFFFF, "alt_alt_alt_board", { /* field match */ TERM }, @@ -373,7 +373,7 @@ TERM }, }, - { PCB_EGKW_SECT_BOARDNET, "boardnet", + { PCB_EGKW_SECT_BOARDNET, 0xFFFF, "boardnet", { /* field match */ TERM }, @@ -392,7 +392,7 @@ TERM }, }, - { PCB_EGKW_SECT_ALT_BOARDNET, "alt_boardnet", + { PCB_EGKW_SECT_ALT_BOARDNET, 0xFFFF, "alt_boardnet", { /* field match */ TERM }, @@ -411,7 +411,7 @@ TERM }, }, - { PCB_EGKW_SECT_ALT_ALT_BOARDNET, "alt_alt_boardnet", + { PCB_EGKW_SECT_ALT_ALT_BOARDNET, 0xFFFF, "alt_alt_boardnet", { /* field match */ TERM }, @@ -430,7 +430,7 @@ TERM }, }, - { PCB_EGKW_SECT_ALT_ALT_ALT_BOARDNET, "alt_alt_alt_boardnet", + { PCB_EGKW_SECT_ALT_ALT_ALT_BOARDNET, 0xFFFF, "alt_alt_alt_boardnet", { /* field match */ TERM }, @@ -449,7 +449,7 @@ TERM }, }, - { PCB_EGKW_SECT_ALT_ALT_ALT_ALT_BOARDNET, "alt_alt_alt_alt_boardnet", + { PCB_EGKW_SECT_ALT_ALT_ALT_ALT_BOARDNET, 0xFFFF, "alt_alt_alt_alt_boardnet", { /* field match */ TERM }, @@ -468,7 +468,7 @@ TERM }, }, - { PCB_EGKW_SECT_SYMBOL, "symbol", + { PCB_EGKW_SECT_SYMBOL, 0xFFFF, "symbol", { /* field match */ TERM }, @@ -485,7 +485,7 @@ TERM }, }, - { PACKAGE, "package", + { PACKAGE, 0xFFFF, "package", { /* field match */ TERM }, @@ -503,7 +503,7 @@ TERM }, }, - { ALT_PACKAGE, "alt_package", + { ALT_PACKAGE, 0xFFFF, "alt_package", { /* field match */ TERM }, @@ -521,7 +521,7 @@ TERM }, }, - { PCB_EGKW_SECT_SCHEMANET, "schemanet", + { PCB_EGKW_SECT_SCHEMANET, 0xFFFF, "schemanet", { /* field match */ TERM }, @@ -539,7 +539,7 @@ TERM }, }, - { PCB_EGKW_SECT_PATH, "path", + { PCB_EGKW_SECT_PATH, 0xFFFF, "path", { /* field match */ TERM }, @@ -555,7 +555,7 @@ TERM }, }, - { POLYGON, "polygon", + { POLYGON, 0xFFFF, "polygon", { /* field match */ TERM }, @@ -579,7 +579,7 @@ TERM }, }, - { ALT_POLYGON, "alt_polygon", + { ALT_POLYGON, 0xFFFF, "alt_polygon", { /* field match */ TERM }, @@ -603,7 +603,7 @@ TERM }, }, - { PCB_EGKW_SECT_LINE, "line", + { PCB_EGKW_SECT_LINE, 0xFFFF, "line", { /* field match */ TERM }, @@ -630,7 +630,7 @@ TERM }, }, - { PCB_EGKW_SECT_ALT_LINE, "alt_line", + { PCB_EGKW_SECT_ALT_LINE, 0xFFFF, "alt_line", { /* field match */ TERM }, @@ -657,7 +657,7 @@ TERM }, }, - { PCB_EGKW_SECT_ALT_ALT_LINE, "alt_alt_line", + { PCB_EGKW_SECT_ALT_ALT_LINE, 0xFFFF, "alt_alt_line", { /* field match */ TERM }, @@ -684,7 +684,7 @@ TERM }, }, - { PCB_EGKW_SECT_ALT_ALT_ALT_LINE, "alt_alt_alt_line", + { PCB_EGKW_SECT_ALT_ALT_ALT_LINE, 0xFFFF, "alt_alt_alt_line", { /* field match */ TERM }, @@ -711,7 +711,7 @@ TERM }, }, - { PCB_EGKW_SECT_ALT_ALT_ALT_ALT_LINE, "alt_alt_alt_alt_line", + { PCB_EGKW_SECT_ALT_ALT_ALT_ALT_LINE, 0xFFFF, "alt_alt_alt_alt_line", { /* field match */ TERM }, @@ -738,7 +738,7 @@ TERM }, }, - { PCB_EGKW_SECT_ALT_ALT_ALT_ALT_ALT_LINE, "alt_alt_alt_alt_alt_line", + { PCB_EGKW_SECT_ALT_ALT_ALT_ALT_ALT_LINE, 0xFFFF, "alt_alt_alt_alt_alt_line", { /* field match */ TERM }, @@ -765,7 +765,7 @@ TERM }, }, - { PCB_EGKW_SECT_ALT_ALT_ALT_ALT_ALT_ALT_LINE, "alt_alt_alt_alt_alt_alt_line", + { PCB_EGKW_SECT_ALT_ALT_ALT_ALT_ALT_ALT_LINE, 0xFFFF, "alt_alt_alt_alt_alt_alt_line", { /* field match */ TERM }, @@ -792,7 +792,7 @@ TERM }, }, - { PCB_EGKW_SECT_ALT_ALT_ALT_ALT_ALT_ALT_ALT_LINE, "alt_alt_alt_alt_alt_alt_alt_line", + { PCB_EGKW_SECT_ALT_ALT_ALT_ALT_ALT_ALT_ALT_LINE, 0xFFFF, "alt_alt_alt_alt_alt_alt_alt_line", { /* field match */ TERM }, @@ -819,7 +819,7 @@ TERM }, }, - { PCB_EGKW_SECT_ARC, "arc", + { PCB_EGKW_SECT_ARC, 0xFFFF, "arc", { /* field match */ TERM }, @@ -846,7 +846,7 @@ TERM }, }, - { CIRCLE, "circle", + { CIRCLE, 0xFFFF, "circle", { /* field match */ TERM }, @@ -862,7 +862,7 @@ TERM }, }, - { ALT_CIRCLE, "alt_circle", + { ALT_CIRCLE, 0xFFFF, "alt_circle", { /* field match */ TERM }, @@ -878,7 +878,7 @@ TERM }, }, - { ALT_ALT_CIRCLE, "alt_alt_circle", + { ALT_ALT_CIRCLE, 0xFFFF, "alt_alt_circle", { /* field match */ TERM }, @@ -894,7 +894,7 @@ TERM }, }, - { RECTANGLE, "rectangle", + { RECTANGLE, 0xFFFF, "rectangle", { /* field match */ TERM }, @@ -911,7 +911,7 @@ TERM }, }, - { ALT_RECTANGLE, "alt_rectangle", + { ALT_RECTANGLE, 0xFFFF, "alt_rectangle", { /* field match */ TERM }, @@ -928,7 +928,7 @@ TERM }, }, - { ALT_ALT_RECTANGLE, "alt_alt_rectangle", + { ALT_ALT_RECTANGLE, 0xFFFF, "alt_alt_rectangle", { /* field match */ TERM }, @@ -945,7 +945,7 @@ TERM }, }, - { PCB_EGKW_SECT_JUNCTION, "junction", + { PCB_EGKW_SECT_JUNCTION, 0xFFFF, "junction", { /* field match */ TERM }, @@ -960,7 +960,7 @@ TERM }, }, - { HOLE, "hole", + { HOLE, 0xFFFF, "hole", { /* field match */ TERM }, @@ -974,7 +974,7 @@ TERM }, }, - { ALT_HOLE, "alt_hole", + { ALT_HOLE, 0xFFFF, "alt_hole", { /* field match */ TERM }, @@ -988,7 +988,7 @@ TERM }, }, - { ALT_ALT_HOLE, "alt_alt_hole", + { ALT_ALT_HOLE, 0xFFFF, "alt_alt_hole", { /* field match */ TERM }, @@ -1002,7 +1002,7 @@ TERM }, }, - { VIA, "via", + { VIA, 0xFFFF, "via", { /* field match */ TERM }, @@ -1020,7 +1020,7 @@ TERM }, }, - { ALT_VIA, "alt_via", + { ALT_VIA, 0xFFFF, "alt_via", { /* field match */ TERM }, @@ -1038,7 +1038,7 @@ TERM }, }, - { PAD, "pad", + { PAD, 0xFFFF, "pad", { /* field match */ TERM }, @@ -1059,7 +1059,7 @@ TERM }, }, - { ALT_PAD, "alt_pad", + { ALT_PAD, 0xFFFF, "alt_pad", { /* field match */ TERM }, @@ -1080,7 +1080,7 @@ TERM }, }, - { ALT_ALT_PAD, "alt_alt_pad", + { ALT_ALT_PAD, 0xFFFF, "alt_alt_pad", { /* field match */ TERM }, @@ -1101,7 +1101,7 @@ TERM }, }, - { SMD, "smd", + { SMD, 0xFFFF, "smd", { /* field match */ TERM }, @@ -1124,7 +1124,7 @@ TERM }, }, - { ALT_SMD, "alt_smd", + { ALT_SMD, 0xFFFF, "alt_smd", { /* field match */ TERM }, @@ -1147,7 +1147,7 @@ TERM }, }, - { PCB_EGKW_SECT_PIN, "pin", + { PCB_EGKW_SECT_PIN, 0xFFFF, "pin", { /* field match */ TERM }, @@ -1168,7 +1168,7 @@ TERM }, }, - { PCB_EGKW_SECT_GATE, "gate", + { PCB_EGKW_SECT_GATE, 0xFFFF, "gate", { /* field match */ TERM }, @@ -1185,7 +1185,7 @@ TERM }, }, - { PACKAGE, "package", + { PACKAGE, 0xFFFF, "package", { /* field match */ TERM }, @@ -1204,7 +1204,7 @@ TERM }, }, - { ALT_PACKAGE, "alt_package", + { ALT_PACKAGE, 0xFFFF, "alt_package", { /* field match */ TERM }, @@ -1223,7 +1223,7 @@ TERM }, }, - { ALT_ALT_PACKAGE, "alt_alt_package", + { ALT_ALT_PACKAGE, 0xFFFF, "alt_alt_package", { /* field match */ TERM }, @@ -1242,7 +1242,7 @@ TERM }, }, - { ALT_ALT_ALT_PACKAGE, "alt_alt_alt_package", + { ALT_ALT_ALT_PACKAGE, 0xFFFF, "alt_alt_alt_package", { /* field match */ TERM }, @@ -1261,7 +1261,7 @@ TERM }, }, - { ALT_ALT_ALT_ALT_PACKAGE, "alt_alt_alt_alt_package", + { ALT_ALT_ALT_ALT_PACKAGE, 0xFFFF, "alt_alt_alt_alt_package", { /* field match */ TERM }, @@ -1280,7 +1280,7 @@ TERM }, }, - { PACKAGE2, "package2", + { PACKAGE2, 0xFFFF, "package2", { /* field match */ TERM }, @@ -1293,7 +1293,7 @@ TERM }, }, - { ALT_PACKAGE2, "alt_package2", + { ALT_PACKAGE2, 0xFFFF, "alt_package2", { /* field match */ TERM }, @@ -1306,7 +1306,7 @@ TERM }, }, - { ALT_ALT_PACKAGE2, "alt_alt_package2", + { ALT_ALT_PACKAGE2, 0xFFFF, "alt_alt_package2", { /* field match */ TERM }, @@ -1319,7 +1319,7 @@ TERM }, }, - { PCB_EGKW_SECT_INSTANCE, "instance", + { PCB_EGKW_SECT_INSTANCE, 0xFFFF, "instance", { /* field match */ TERM }, @@ -1340,7 +1340,7 @@ TERM }, }, - { TEXT, "text", /* basic text block */ + { TEXT, 0xFFFF, "text", /* basic text block */ { /* field match */ TERM }, @@ -1364,7 +1364,7 @@ TERM }, }, - { ALT_TEXT, "alt_text", /* basic text block */ + { ALT_TEXT, 0xFFFF, "alt_text", /* basic text block */ { /* field match */ TERM }, @@ -1388,7 +1388,7 @@ TERM }, }, - { ALT_ALT_TEXT, "alt_alt_text", /* basic text block */ + { ALT_ALT_TEXT, 0xFFFF, "alt_alt_text", /* basic text block */ { /* field match */ TERM }, @@ -1412,7 +1412,7 @@ TERM }, }, - { ALT_ALT_ALT_TEXT, "alt_alt_alt_text", /* basic text block */ + { ALT_ALT_ALT_TEXT, 0xFFFF, "alt_alt_alt_text", /* basic text block */ { /* field match */ TERM }, @@ -1436,7 +1436,7 @@ TERM }, }, - { PCB_EGKW_SECT_NETBUSLABEL, "netbuslabel", /* text base section equiv. */ + { PCB_EGKW_SECT_NETBUSLABEL, 0xFFFF, "netbuslabel", /* text base section equiv. */ { /* field match */ TERM }, @@ -1460,7 +1460,7 @@ TERM }, }, - { PCB_EGKW_SECT_SMASHEDNAME, "smashedname", /* text base section equiv. */ + { PCB_EGKW_SECT_SMASHEDNAME, 0xFFFF, "smashedname", /* text base section equiv. */ { /* field match */ TERM }, @@ -1484,7 +1484,7 @@ TERM }, }, - { PCB_EGKW_SECT_ALT_SMASHEDNAME, "alt_smashedname", /* text base section equiv. */ + { PCB_EGKW_SECT_ALT_SMASHEDNAME, 0xFFFF, "alt_smashedname", /* text base section equiv. */ { /* field match */ TERM }, @@ -1508,7 +1508,7 @@ TERM }, }, - { PCB_EGKW_SECT_ALT_ALT_SMASHEDNAME, "alt_alt_smashedname", /* text base section equiv. */ + { PCB_EGKW_SECT_ALT_ALT_SMASHEDNAME, 0xFFFF, "alt_alt_smashedname", /* text base section equiv. */ { /* field match */ TERM }, @@ -1532,7 +1532,7 @@ TERM }, }, - { PCB_EGKW_SECT_ALT_ALT_ALT_SMASHEDNAME, "alt_alt_alt_smashedname", /* text base section equiv. */ + { PCB_EGKW_SECT_ALT_ALT_ALT_SMASHEDNAME, 0xFFFF, "alt_alt_alt_smashedname", /* text base section equiv. */ { /* field match */ TERM }, @@ -1556,7 +1556,7 @@ TERM }, }, - { PCB_EGKW_SECT_SMASHEDVALUE, "smashedvalue", /* text base section equiv. */ + { PCB_EGKW_SECT_SMASHEDVALUE, 0xFFFF, "smashedvalue", /* text base section equiv. */ { /* field match */ TERM }, @@ -1580,7 +1580,7 @@ TERM }, }, - { PCB_EGKW_SECT_ALT_SMASHEDVALUE, "alt_smashedvalue", /* text base section equiv. */ + { PCB_EGKW_SECT_ALT_SMASHEDVALUE, 0xFFFF, "alt_smashedvalue", /* text base section equiv. */ { /* field match */ TERM }, @@ -1604,7 +1604,7 @@ TERM }, }, - { PCB_EGKW_SECT_ALT_ALT_SMASHEDVALUE, "alt_alt_smashedvalue", /* text base section equiv. */ + { PCB_EGKW_SECT_ALT_ALT_SMASHEDVALUE, 0xFFFF, "alt_alt_smashedvalue", /* text base section equiv. */ { /* field match */ TERM }, @@ -1628,7 +1628,7 @@ TERM }, }, - { PCB_EGKW_SECT_ALT_ALT_ALT_SMASHEDVALUE, "alt_alt_alt_smashedvalue", /* text base section equiv. */ + { PCB_EGKW_SECT_ALT_ALT_ALT_SMASHEDVALUE, 0xFFFF, "alt_alt_alt_smashedvalue", /* text base section equiv. */ { /* field match */ TERM }, @@ -1652,13 +1652,13 @@ TERM }, }, - { PCB_EGKW_SECT_PACKAGEVARIANT }, - { PCB_EGKW_SECT_DEVICE }, - { PCB_EGKW_SECT_PART }, - { PCB_EGKW_SECT_SCHEMABUS }, - { PCB_EGKW_SECT_VARIANTCONNECTIONS }, - { PCB_EGKW_SECT_SCHEMACONNECTION }, - { PCB_EGKW_SECT_BOARDCONNECTION, "boardconnection", + { PCB_EGKW_SECT_PACKAGEVARIANT, 0xFFFF }, + { PCB_EGKW_SECT_DEVICE, 0xFFFF }, + { PCB_EGKW_SECT_PART, 0xFFFF }, + { PCB_EGKW_SECT_SCHEMABUS, 0xFFFF }, + { PCB_EGKW_SECT_VARIANTCONNECTIONS, 0xFFFF }, + { PCB_EGKW_SECT_SCHEMACONNECTION, 0xFFFF }, + { PCB_EGKW_SECT_BOARDCONNECTION, 0xFFFF, "boardconnection", { /* field match */ TERM }, @@ -1671,7 +1671,7 @@ TERM }, }, - { PCB_EGKW_SECT_ALT_BOARDCONNECTION, "alt_boardconnection", + { PCB_EGKW_SECT_ALT_BOARDCONNECTION, 0xFFFF, "alt_boardconnection", { /* field match */ TERM }, @@ -1684,7 +1684,7 @@ TERM }, }, - { PCB_EGKW_SECT_ALT_ALT_BOARDCONNECTION, "alt_alt_boardconnection", + { PCB_EGKW_SECT_ALT_ALT_BOARDCONNECTION, 0xFFFF, "alt_alt_boardconnection", { /* field match */ TERM }, @@ -1697,7 +1697,7 @@ TERM }, }, - { PCB_EGKW_SECT_ALT_ALT_ALT_BOARDCONNECTION, "alt_alt_alt_boardconnection", + { PCB_EGKW_SECT_ALT_ALT_ALT_BOARDCONNECTION, 0xFFFF, "alt_alt_alt_boardconnection", { /* field match */ TERM }, @@ -1710,7 +1710,7 @@ TERM }, }, - { PCB_EGKW_SECT_ALT_ALT_ALT_ALT_BOARDCONNECTION, "alt_alt_alt_alt_boardconnection", + { PCB_EGKW_SECT_ALT_ALT_ALT_ALT_BOARDCONNECTION, 0xFFFF, "alt_alt_alt_alt_boardconnection", { /* field match */ TERM }, @@ -1723,7 +1723,7 @@ TERM }, }, - { PCB_EGKW_SECT_SMASHEDPART, "smashedpart", /* same as text basesection */ + { PCB_EGKW_SECT_SMASHEDPART, 0xFFFF, "smashedpart", /* same as text basesection */ { /* field match */ TERM }, @@ -1747,7 +1747,7 @@ TERM }, }, - { PCB_EGKW_SECT_SMASHEDGATE, "smashedgate", /* same as text basesection */ + { PCB_EGKW_SECT_SMASHEDGATE, 0xFFFF, "smashedgate", /* same as text basesection */ { /* field match */ TERM }, @@ -1771,7 +1771,7 @@ TERM }, }, - { ATTRIBUTE, "attribute", /* same as text basesection */ + { ATTRIBUTE, 0xFFFF, "attribute", /* same as text basesection */ { /* field match */ TERM }, @@ -1795,7 +1795,7 @@ TERM }, }, - { ALT_ATTRIBUTE, "alt_attribute", /* same as text basesection */ + { ALT_ATTRIBUTE, 0xFFFF, "alt_attribute", /* same as text basesection */ { /* field match */ TERM }, @@ -1819,7 +1819,7 @@ TERM }, }, - { PCB_EGKW_SECT_ATTRIBUTEVALUE, "attribute-value", + { PCB_EGKW_SECT_ATTRIBUTEVALUE, 0xFFFF, "attribute-value", { /* field match */ TERM }, @@ -1832,7 +1832,7 @@ TERM }, }, - { PCB_EGKW_SECT_FRAME, "frame", + { PCB_EGKW_SECT_FRAME, 0xFFFF, "frame", { /* field match */ TERM }, @@ -1852,7 +1852,7 @@ TERM }, }, - { PCB_EGKW_SECT_SMASHEDXREF, "smashedxref", + { PCB_EGKW_SECT_SMASHEDXREF, 0xFFFF, "smashedxref", { /* field match */ TERM }, @@ -1878,7 +1878,7 @@ }, /* unknown leaves */ - { 0x5300 }, + { 0x5300, 0xFFFF }, /* end of table */ { 0 }