Index: eagle/eagle_bin/test_parser/eagle_bin.c
===================================================================
--- eagle/eagle_bin/test_parser/eagle_bin.c	(revision 9559)
+++ eagle/eagle_bin/test_parser/eagle_bin.c	(revision 9560)
@@ -57,7 +57,7 @@
 #define TERM {0}
 
 static const pcb_eagle_script_t pcb_eagle_script[] = {
-	{ PCB_EGKW_SECT_START, 0xFFFF, "start",
+	{ PCB_EGKW_SECT_START, 0xFF7F, "start",
 		{ /* field match */
 			TERM
 		},
@@ -80,29 +80,6 @@
 			TERM
 		},
 	},
-	{ PCB_EGKW_SECT_ALT_START, 0xFFFF, "alt_start",
-		{ /* field match */
-			TERM
-		},
-		{ /* subsection sizes */
-/*			{2, 2, SS_DIRECT, NULL},*/
-			{4, 4, SS_RECURSIVE_MINUS_1, NULL},
-			TERM
-		},
-		{ /* attributes */
-			{"subsecs", T_INT, 2, 2},
-			{"numsecs", T_INT, 4, 4},
-			{"subsecsMSB", T_INT, 3, 1},
-			{"subsecsLSB", T_INT, 2, 1},
-			{"numsecsMSB2", T_INT, 7, 1},
-			{"numsecsMSB1", T_INT, 6, 1},
-			{"numsecsMSB0", T_INT, 5, 1},
-			{"numsecsLSB", T_INT, 4, 1},
-			{"v1", T_INT, 8, 1},
-			{"v2", T_INT, 9, 1},
-			TERM
-		},
-	},
 	{ PCB_EGKW_SECT_UKNOWN11, 0xFFFF },
 	{ PCB_EGKW_SECT_GRID, 0xFFFF, "grid",
 		{ /* field match */
@@ -122,7 +99,7 @@
 			TERM
 		},
 	},
-	{ PCB_EGKW_SECT_LAYERS, 0xFFFF, "layers",
+	{ PCB_EGKW_SECT_LAYERS, 0xFF7F, "layers",
 		{ /* field match */
 			TERM
 		},
@@ -141,25 +118,6 @@
 			TERM
 		},
 	},
-	{ PCB_EGKW_SECT_ALT_LAYERS, 0xFFFF, "alt_layers",
-		{ /* field match */
-			TERM
-		},
-		{ /* subsection sizes */
-			TERM
-		},
-		{ /* attributes */
-			{"side", T_BMB, 2, 0x10},
-			{"visible", T_UBF, 2, BITFIELD(1, 2, 3)},
-			{"available", T_BMB, 2, 0x02},
-			{"layer",T_INT, 3, 1},
-			{"other",T_INT, 4, 1},
-			{"fill", T_UBF, 5, BITFIELD(1, 0, 3)},
-			{"color",T_UBF, 6, BITFIELD(1, 0, 5)},
-			{"name", T_STR, 15, 9},
-			TERM
-		},
-	},
 	{ PCB_EGKW_SECT_SCHEMA, 0xFFFF, "schema",
 		{ /* field match */
 			TERM
@@ -219,7 +177,7 @@
 			TERM
 		},
 	},
-	{ PCB_EGKW_SECT_PACKAGES, 0xFFFF, "packages",
+	{ PCB_EGKW_SECT_PACKAGES, 0xFF5F, "packages",
 		{ /* field match */
 			TERM
 		},
@@ -235,38 +193,6 @@
 			TERM
 		},
 	},
-	{ PCB_EGKW_SECT_ALT_PACKAGES, 0xFFFF, "alt_packages",
-		{ /* field match */
-			TERM
-		},
-		{ /* subsection sizes */
-			{4, 4, SS_RECURSIVE, NULL},
-			TERM
-		},
-		{ /* attributes */
-			{"subsects", T_INT, 4, 4},
-			{"children", T_INT, 8, 2},
-			{"desc",  T_STR, 10, 6},
-			{"libname",  T_STR, 16, 8},
-			TERM
-		},
-	},
-	{ PCB_EGKW_SECT_ALT_ALT_PACKAGES, 0xFFFF, "alt_alt_packages",
-		{ /* field match */
-			TERM
-		},
-		{ /* subsection sizes */
-			{4, 4, SS_RECURSIVE, NULL},
-			TERM
-		},
-		{ /* attributes */
-			{"subsects", T_INT, 4, 4},
-			{"children", T_INT, 8, 2},
-			{"desc",  T_STR, 10, 6},
-			{"libname",  T_STR, 16, 8},
-			TERM
-		},
-	},
 	{ PCB_EGKW_SECT_SCHEMASHEET, 0xFFFF, "schemasheet",
 		{ /* field match */
 			TERM
@@ -286,7 +212,7 @@
 			TERM
 		},
 	},
-	{ PCB_EGKW_SECT_BOARD, 0xFFFF, "board",
+	{ PCB_EGKW_SECT_BOARD, 0xFF37, "board",
 		{ /* field match */
 			TERM
 		},
@@ -308,77 +234,11 @@
 			TERM
 		},
 	},
-	{ PCB_EGKW_SECT_ALT_BOARD, 0xFFFF, "alt_board",
+	{ PCB_EGKW_SECT_SIGNAL, 0xFFB7, "signal",
 		{ /* field match */
 			TERM
 		},
 		{ /* subsection sizes */
-			{12, 4, SS_RECURSIVE, NULL}, /* lib */
-			{2,  2, SS_DIRECT, NULL},    /* globals */
-			{16, 4, SS_RECURSIVE, NULL}, /* package refs */
-			{20, 4, SS_RECURSIVE, NULL}, /* nets */
-			TERM
-		},
-		{ /* attributes */
-			{"minx",  T_INT, 4, 2},
-			{"miny",  T_INT, 6, 2},
-			{"maxx",  T_INT, 8, 2},
-			{"maxy",  T_INT, 10, 2},
-			{"defsubsecs",  T_INT, 12, 4},
-			{"pacsubsecs",  T_INT, 16, 4},
-			{"netsubsecs",  T_INT, 20, 4},
-			TERM
-		},
-	},
-	{ PCB_EGKW_SECT_ALT_ALT_BOARD, 0xFFFF, "alt_alt_board",
-		{ /* field match */
-			TERM
-		},
-		{ /* subsection sizes */
-			{12, 4, SS_RECURSIVE, NULL}, /* lib */
-			{2,  2, SS_DIRECT, NULL},    /* globals */
-			{16, 4, SS_RECURSIVE, NULL}, /* package refs */
-			{20, 4, SS_RECURSIVE, NULL}, /* nets */
-			TERM
-		},
-		{ /* attributes */
-			{"minx",  T_INT, 4, 2},
-			{"miny",  T_INT, 6, 2},
-			{"maxx",  T_INT, 8, 2},
-			{"maxy",  T_INT, 10, 2},
-			{"defsubsecs",  T_INT, 12, 4},
-			{"pacsubsecs",  T_INT, 16, 4},
-			{"netsubsecs",  T_INT, 20, 4},
-			TERM
-		},
-	},
-	{ PCB_EGKW_SECT_ALT_ALT_ALT_BOARD, 0xFFFF, "alt_alt_alt_board",
-		{ /* field match */
-			TERM
-		},
-		{ /* subsection sizes */
-			{12, 4, SS_RECURSIVE, NULL}, /* lib */
-			{2,  2, SS_DIRECT, NULL},    /* globals */
-			{16, 4, SS_RECURSIVE, NULL}, /* package refs */
-			{20, 4, SS_RECURSIVE, NULL}, /* nets */
-			TERM
-		},
-		{ /* attributes */
-			{"minx",  T_INT, 4, 2},
-			{"miny",  T_INT, 6, 2},
-			{"maxx",  T_INT, 8, 2},
-			{"maxy",  T_INT, 10, 2},
-			{"defsubsecs",  T_INT, 12, 4},
-			{"pacsubsecs",  T_INT, 16, 4},
-			{"netsubsecs",  T_INT, 20, 4},
-			TERM
-		},
-	},
-	{ PCB_EGKW_SECT_SIGNAL, 0xFFFF, "signal",
-		{ /* field match */
-			TERM
-		},
-		{ /* subsection sizes */
 			{2, 2, SS_DIRECT, NULL},
 			TERM
 		},
@@ -393,82 +253,6 @@
 			TERM
 		},
 	},
-	{ PCB_EGKW_SECT_ALT_SIGNAL, 0xFFFF, "alt_signal",
-		{ /* field match */
-			TERM
-		},
-		{ /* subsection sizes */
-			{2, 2, SS_DIRECT, NULL},
-			TERM
-		},
-		{ /* attributes */
-			{"minx",  T_INT, 4, 2},
-			{"miny",  T_INT, 6, 2},
-			{"maxx",  T_INT, 8, 2},
-			{"maxy",  T_INT, 10, 2},
-			{"airwires",  T_BMB, 12, 0x02},
-			{"netclass",  T_UBF, 13, BITFIELD(1, 0, 3)},
-			{"name",  T_INT, 16, 8},
-			TERM
-		},
-	},
-	{ PCB_EGKW_SECT_ALT_ALT_SIGNAL, 0xFFFF, "alt_alt_signal",
-		{ /* field match */
-			TERM
-		},
-		{ /* subsection sizes */
-			{2, 2, SS_DIRECT, NULL},
-			TERM
-		},
-		{ /* attributes */
-			{"minx",  T_INT, 4, 2},
-			{"miny",  T_INT, 6, 2},
-			{"maxx",  T_INT, 8, 2},
-			{"maxy",  T_INT, 10, 2},
-			{"airwires",  T_BMB, 12, 0x02},
-			{"netclass",  T_UBF, 13, BITFIELD(1, 0, 3)},
-			{"name",  T_INT, 16, 8},
-			TERM
-		},
-	},
-	{ PCB_EGKW_SECT_ALT_ALT_ALT_SIGNAL, 0xFFFF, "alt_alt_alt_signal",
-		{ /* field match */
-			TERM
-		},
-		{ /* subsection sizes */
-			{2, 2, SS_DIRECT, NULL},
-			TERM
-		},
-		{ /* attributes */
-			{"minx",  T_INT, 4, 2},
-			{"miny",  T_INT, 6, 2},
-			{"maxx",  T_INT, 8, 2},
-			{"maxy",  T_INT, 10, 2},
-			{"airwires",  T_BMB, 12, 0x02},
-			{"netclass",  T_UBF, 13, BITFIELD(1, 0, 3)},
-			{"name",  T_INT, 16, 8},
-			TERM
-		},
-	},
-	{ PCB_EGKW_SECT_ALT_ALT_ALT_ALT_SIGNAL, 0xFFFF, "alt_alt_alt_alt_signal",
-		{ /* field match */
-			TERM
-		},
-		{ /* subsection sizes */
-			{2, 2, SS_DIRECT, NULL},
-			TERM
-		},
-		{ /* attributes */
-			{"minx",  T_INT, 4, 2},
-			{"miny",  T_INT, 6, 2},
-			{"maxx",  T_INT, 8, 2},
-			{"maxy",  T_INT, 10, 2},
-			{"airwires",  T_BMB, 12, 0x02},
-			{"netclass",  T_UBF, 13, BITFIELD(1, 0, 3)},
-			{"name",  T_INT, 16, 8},
-			TERM
-		},
-	},
 	{ PCB_EGKW_SECT_SYMBOL, 0xFFFF, "symbol",
 		{ /* field match */
 			TERM