r34454
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| igor2 | 2021-04-12T17:40:13.076311Z
| [core] -Update: convert the default boards to lihata v8 - use explicit padstack vias and text scale in routing style
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r28228
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| igor2 | 2019-11-12T03:05:17.206451Z
| [core] -Fix: default boards: group name for top and bottom assy should have _ for separator, not -, for consistency
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r16227
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| igor2 | 2018-04-07T07:48:19.037998Z
| [conf] -Cleanup: remove drc and conf sections from the default boards; default config should be coming from internal and system config files so that the user can easily override them (config settings coming from the default board have the DESIGN role that is hard to override)
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r14517
| file changeset diff or repo changeset diff
| igor2 | 2018-02-06T03:04:29.099310Z
| [core] -Fix: default board has no space in the name of the global outline layer and the layer is not marked as internal
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r13580
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| igor2 | 2017-12-21T14:18:27.089093Z
| [core] -Update: default pcb's are liahat v4 - just in case they are directly loaded and saved as a new file, the new files would also inherit the latest version
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r11724
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| igor2 | 2017-09-23T11:47:42.162578Z
| [data] -Change: switch over from old default.pcb and implicit mask/paste layers to new, lihata based 2 and 4 layer defaults
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