r34454 file changeset diff or repo changeset diff igor22021-04-12T17:40:13.076311Z
 
[core] -Update: convert the default boards to lihata v8 - use explicit padstack vias and text scale in routing style
r32776 file changeset diff or repo changeset diff igor22020-09-17T06:39:29.484789Z
 
[core] -Update: default boards are of lihata board v7, so plain save will not downgrade new boards to v6
r29913 file changeset diff or repo changeset diff igor22020-02-28T06:56:06.899687Z
 
[layer] -Add: default board: {l s} and {l x} selects top abdn bottom silk
r29912 file changeset diff or repo changeset diff igor22020-02-28T06:42:34.125188Z
 
[layer] -Add: default board file copper layer key bindings
r28927 file changeset diff or repo changeset diff igor22019-12-23T11:03:19.129714Z
 
[core] -Update: default boards have substrate thickness set to 1.6mm finished
r28228 file changeset diff or repo changeset diff igor22019-11-12T03:05:17.206451Z
 
[core] -Fix: default boards: group name for top and bottom assy should have _ for separator, not -, for consistency
r27265 file changeset diff or repo changeset diff igor22019-08-22T06:43:53.325636Z
 
[layer] -Cleanup: default board layer table indentation
r27264 file changeset diff or repo changeset diff igor22019-08-22T06:41:48.587392Z
 
[layer] -Fix: default board, 2 sided: remove excess layer attributes
r27263 file changeset diff or repo changeset diff igor22019-08-22T06:35:32.393433Z
 
[layer] -Add: explicit fab layer in default 2 and 4 layer boards
r27261 file changeset diff or repo changeset diff igor22019-08-22T06:31:49.310623Z
 
[layer] -Fix: typo: bottom assy should be on the bottom side in default boards
r27260 file changeset diff or repo changeset diff igor22019-08-22T06:30:25.860018Z
 
[layer] -Change: default 2 and 4 layer boards have assy layer groups with init-invis set
r27250 file changeset diff or repo changeset diff igor22019-08-21T06:05:21.276758Z
 
[core] -Add: default pcb now includes explicit assy layers
r19610 file changeset diff or repo changeset diff igor22018-09-27T06:35:15.889662Z
 
[core] -Add: bump default2.lht to v6 and add mech layers
r17155 file changeset diff or repo changeset diff avigne2018-05-31T10:24:28.396309Z
 
[core] -Fix: 2 layer default board message: Broken layer stackup: group->layer backlink for layer 4
r17140 file changeset diff or repo changeset diff igor22018-05-29T06:13:04.534012Z
 
[core] -Fix: 2 layer default board typo sent a singal layer into the outline group
r16227 file changeset diff or repo changeset diff igor22018-04-07T07:48:19.037998Z
 
[conf] -Cleanup: remove drc and conf sections from the default boards; default config should be coming from internal and system config files so that the user can easily override them (config settings coming from the default board have the DESIGN role that is hard to override)
r16216 file changeset diff or repo changeset diff igor22018-04-07T06:50:56.096041Z
 
[core] -Fix: attribute pollution from default boards - no need to set grid unit as attribute
r14517 file changeset diff or repo changeset diff igor22018-02-06T03:04:29.099310Z
 
[core] -Fix: default board has no space in the name of the global outline layer and the layer is not marked as internal
r13580 file changeset diff or repo changeset diff igor22017-12-21T14:18:27.089093Z
 
[core] -Update: default pcb's are liahat v4 - just in case they are directly loaded and saved as a new file, the new files would also inherit the latest version
r11724 file changeset diff or repo changeset diff igor22017-09-23T11:47:42.162578Z
 
[data] -Change: switch over from old default.pcb and implicit mask/paste layers to new, lihata based 2 and 4 layer defaults

Command line to view the complete history:
svn log -v svn://svn.repo.hu/pcb-rnd//trunk/src/default2.lht